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Message-ID: <alpine.DEB.2.02.1506042258530.12316@utopia.booyaka.com>
Date: Thu, 4 Jun 2015 23:02:25 +0000 (UTC)
From: Paul Walmsley <paul@...an.com>
To: Boris Brezillon <boris.brezillon@...e-electrons.com>
cc: Mike Turquette <mturquette@...aro.org>,
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Subject: Re: [PATCH v2 1/2] clk: change clk_ops' ->round_rate() prototype
Hi folks
just a brief comment on this one:
On Thu, 30 Apr 2015, Boris Brezillon wrote:
> Clock rates are stored in an unsigned long field, but ->round_rate()
> (which returns a rounded rate from a requested one) returns a long
> value (errors are reported using negative error codes), which can lead
> to long overflow if the clock rate exceed 2Ghz.
>
> Change ->round_rate() prototype to return 0 or an error code, and pass the
> requested rate as a pointer so that it can be adjusted depending on
> hardware capabilities.
...
> diff --git a/Documentation/clk.txt b/Documentation/clk.txt
> index 0e4f90a..fca8b7a 100644
> --- a/Documentation/clk.txt
> +++ b/Documentation/clk.txt
> @@ -68,8 +68,8 @@ the operations defined in clk.h:
> int (*is_enabled)(struct clk_hw *hw);
> unsigned long (*recalc_rate)(struct clk_hw *hw,
> unsigned long parent_rate);
> - long (*round_rate)(struct clk_hw *hw,
> - unsigned long rate,
> + int (*round_rate)(struct clk_hw *hw,
> + unsigned long *rate,
> unsigned long *parent_rate);
> long (*determine_rate)(struct clk_hw *hw,
> unsigned long rate,
I'd suggest that we should probably go straight to 64-bit rates. There
are already plenty of clock sources that can generate rates higher than
4GiHz.
- Paul
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