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Message-ID: <20150605061612.GA16797@gmail.com>
Date: Fri, 5 Jun 2015 08:16:13 +0200
From: Ingo Molnar <mingo@...nel.org>
To: George Spelvin <linux@...izon.com>
Cc: adrian.hunter@...el.com, ak@...ux.intel.com, hpa@...or.com,
linux-kernel@...r.kernel.org, luto@...capital.net,
tglx@...utronix.de, torvalds@...ux-foundation.org
Subject: Re: [PATCH RFC] x86, tsc: Allow for high latency in
quick_pit_calibrate()
* George Spelvin <linux@...izon.com> wrote:
> It's running at 3.4 GHz, so I expect 729478 ticks per 256 PIT counts, and 415039
> ticks per 8192 Hz RTC tick.
> (PIT reads are 1353 ns each, while RTC reads are 1142 ns.)
>
> RTC edge at 99172986783, delta 0, range 7764, iter 7
> RTC edge at 99173401719, delta 414936, range 7764, iter 106
> RTC edge at 99173816543, delta 414824, range 7764, iter 106
> RTC edge at 99174231391, delta 414848, range 7764, iter 106
> RTC edge at 99174646119, delta 414728, range 7740, iter 106
> +static inline unsigned
> +rtc_wait_bit(u64 *tscp, unsigned long *deltap)
> +{
> + int count = 0;
> + u64 prev_tsc, tsc = 0;
> +
> + do {
> + if (++count > 5000)
> + return 0;
> + prev_tsc = tsc;
> + tsc = get_cycles();
> + } while (~inb(RTC_PORT(1)) & RTC_PF); /* Wait for bit 6 to be set */
> + *deltap = get_cycles() - prev_tsc;
> + *tscp = tsc;
> +/* This is skanky stuff that requries rewritten RTC locking to do properly */
[ Note that no RTC locking is needed so early during bootup: this is the boot CPU
only, with only a single task running, guaranteed. ]
So your code is very close to how I did the RTC sampling, except that I got:
[ 0.000000] tsc: RTC edge 57 from 0 to 64, at 29694678517, delta: 246360, jitter: 2456, loops: 7, 35194 cycles/loop
[ 0.000000] tsc: RTC edge 58 from 0 to 64, at 29695169485, delta: 490968, jitter: 244608, loops: 118, 4160 cycles/loop
[ 0.000000] tsc: RTC edge 59 from 0 to 64, at 29695413981, delta: 244496, jitter: -246472, loops: 6, 40749 cycles/loop
[ 0.000000] tsc: RTC edge 60 from 0 to 64, at 29695660661, delta: 246680, jitter: 2184, loops: 7, 35240 cycles/loop
[ 0.000000] tsc: RTC edge 61 from 0 to 64, at 29695904853, delta: 244192, jitter: -2488, loops: 6, 40698 cycles/loop
[ 0.000000] tsc: RTC edge 62 from 0 to 64, at 29696151141, delta: 246288, jitter: 2096, loops: 7, 35184 cycles/loop
[ 0.000000] tsc: RTC edge 63 from 0 to 64, at 29696396445, delta: 245304, jitter: -984, loops: 6, 40884 cycles/loop
[ 0.000000] tsc: RTC edge 64 from 0 to 64, at 29696642669, delta: 246224, jitter: 920, loops: 7, 35174 cycles/loop
[ 0.000000] tsc: RTC edge 65 from 0 to 64, at 29696887245, delta: 244576, jitter: -1648, loops: 6, 40762 cycles/loop
[ 0.000000] tsc: RTC edge 66 from 0 to 64, at 29697377909, delta: 490664, jitter: 246088, loops: 117, 4193 cycles/loop
[ 0.000000] tsc: RTC edge 67 from 0 to 64, at 29697622701, delta: 244792, jitter: -245872, loops: 6, 40798 cycles/loop
[ 0.000000] tsc: RTC edge 68 from 0 to 64, at 29697868773, delta: 246072, jitter: 1280, loops: 7, 35153 cycles/loop
[ 0.000000] tsc: RTC edge 69 from 0 to 64, at 29700569301, delta: 2700528, jitter: 2454456, loops: 13, 207732 cycles/loop
[ 0.000000] tsc: RTC edge 70 from 0 to 64, at 29700813805, delta: 244504, jitter: -2456024, loops: 6, 40750 cycles/loop
[ 0.000000] tsc: RTC edge 71 from 0 to 64, at 29701060125, delta: 246320, jitter: 1816, loops: 7, 35188 cycles/loop
[ 0.000000] tsc: RTC edge 72 from 0 to 64, at 29701550189, delta: 490064, jitter: 243744, loops: 117, 4188 cycles/loop
[ 0.000000] tsc: RTC edge 73 from 0 to 64, at 29701796677, delta: 246488, jitter: -243576, loops: 7, 35212 cycles/loop
[ 0.000000] tsc: RTC edge 74 from 0 to 64, at 29702040829, delta: 244152, jitter: -2336, loops: 6, 40692 cycles/loop
[ 0.000000] tsc: RTC edge 75 from 0 to 64, at 29702287597, delta: 246768, jitter: 2616, loops: 7, 35252 cycles/loop
[ 0.000000] tsc: RTC edge 76 from 0 to 64, at 29702531741, delta: 244144, jitter: -2624, loops: 6, 40690 cycles/loop
[ 0.000000] tsc: RTC edge 77 from 0 to 64, at 29702778341, delta: 246600, jitter: 2456, loops: 7, 35228 cycles/loop
[ 0.000000] tsc: RTC edge 78 from 0 to 64, at 29703022661, delta: 244320, jitter: -2280, loops: 6, 40720 cycles/loop
[ 0.000000] tsc: RTC edge 79 from 0 to 64, at 29703514245, delta: 491584, jitter: 247264, loops: 118, 4165 cycles/loop
[ 0.000000] tsc: RTC edge 80 from 0 to 64, at 29703759165, delta: 244920, jitter: -246664, loops: 6, 40820 cycles/loop
[ 0.000000] tsc: RTC edge 81 from 0 to 64, at 29704005397, delta: 246232, jitter: 1312, loops: 7, 35176 cycles/loop
[ 0.000000] tsc: RTC edge 82 from 0 to 64, at 29704249589, delta: 244192, jitter: -2040, loops: 6, 40698 cycles/loop
note the 'loops' column. When it's around 117, then the read cost corresponds
roughly to the cheap-ish INB cost you have measured: 4188 cycles/loop.
But note the frequent 30-40k cycles/loop outliers. They dominate the measurement
so filtering might not help.
And this is on a 'boring' 10 years old PC (Nvidia CK804 southbridge), with no HPET
and nothing particularly fancy that I'm aware of. I tried this system first
because I expected it to work and expected problems (with RTCs being emulated via
the HPET) on more modern systems.
If the RTC polling method is not reliable here, it might be doubly problematic on
other systems.
IRQ based RTC calibration worked a lot better, but is problematic from the boot
dependencing POV. It's not unsolvable, but not trivial either - and I'd rather
prefer trivial (polling) methods so early during the bootup!
Thanks,
Ingo
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