linux-kernel - [PATCH v2 0/2] staging: rtl8723au: core: endianness issues

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Message-Id: <1433724182-657-1-git-send-email-ddecotig@gmail.com>
Date:	Sun,  7 Jun 2015 17:43:00 -0700
From:	David Decotigny <ddecotig@...il.com>
To:	Larry Finger <Larry.Finger@...inger.net>,
	Jes Sorensen <Jes.Sorensen@...hat.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	linux-wireless@...r.kernel.org, devel@...verdev.osuosl.org,
	linux-kernel@...r.kernel.org
Cc:	Joe Perches <joe@...ches.com>,
	Dan Carpenter <dan.carpenter@...cle.com>,
	David Decotigny <ddecotig@...il.com>
Subject: [PATCH v2 0/2] staging: rtl8723au: core: endianness issues

The code shows a couple inconsistencies (described in commit
descriptions) which would not be an issue on little-endian cpus, but
could cause breakage on non-LE cpus. Note: I could not test on real
hardware, these patches created based on sparse reports.

Hostory:
  - resending the same patches to correct recipients, only changed
    commit descriptions (credits to Dan Carpenter)

############################################
# Patch Set Summary:

David Decotigny (2):
  staging: rtl8723au: core: avoid bitwise arithmetic with forced
    endianness
  staging: rtl8723au: core: remove redundant endianness conversion

 drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

-- 
2.2.0.rc0.207.ga3a616c

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