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Date:	Wed, 10 Jun 2015 10:40:51 +0800
From:	Huang Rui <>
To:	Borislav Petkov <>, Andy Lutomirski <>
CC:	"Xue, Ken" <>, Thomas Gleixner <>,
	"Li, Tony" <>, "" <>,
	John Stultz <>,
	Aaron Lu <>,
	"Rafael J. Wysocki" <>,
	Frédéric Weisbecker <>,
	"Suthikulpanit, Suravee" <>,
	Fengguang Wu <>,
	"Len Brown" <>,
	"" <>,
	Peter Zijlstra <>
Subject: Re: [PATCH v2 1/4] x86, mwaitt: add monitorx and mwaitx instruction

On Tue, Jun 09, 2015 at 07:06:14PM +0200, Borislav Petkov wrote:
> On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote:
> > [1] For those who weren't bitten by this repeatedly, modern Intel CPUs
> > (at least Sandy Bridge, anyway) will, by default, detect when all
> > cores are in C1 or deeper, think to themselves "wow, the OS selected
> > C1 -- it must want a very deep sleep indeed", and put the whole
> > package into some kind of deep sleep state.  The subsequent wakeup
> > takes tens of milliseconds.  Doing this in udelay would be awful.
> That's a good point. Reportedly, the current MWAITX enters something
> between C0 and C1 but the way I understood it, going forward, it will
> enter deeper sleep states.
> So for shallow C-states, your idle enter/exit latency is low enough but
> I'd guess deeper states would be a problem.

Andy, Boris, that's right. Thanks. :)
If MWAITX will enter C1 and restore back repeatedly. It will impact
the accuracy of delay. I will ask HW designer to check if it already
has configuration to control the target power state.

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