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Message-ID: <20150616091619.GA17817@leverpostej>
Date: Tue, 16 Jun 2015 10:16:19 +0100
From: Mark Rutland <mark.rutland@....com>
To: Kyle Huey <me@...ehuey.com>
Cc: Rob Herring <robh+dt@...nel.org>, Pawel Moll <Pawel.Moll@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
Stephen Warren <swarren@...dotorg.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Jon Hunter <jonathanh@...dia.com>,
Kyle Huey <khuey@...ehuey.com>
Subject: Re: [PATCH v2] ARM: tegra124: pmu support
On Mon, Jun 15, 2015 at 07:46:08PM +0100, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p. This patch was tested on a Jetson TK1.
>
> Signed-off-by: Kyle Huey <khuey@...ehuey.com>
> ---
> arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>
> cpu@3 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <3>;
> };
> };
>
> + pmu {
> + compatible = "arm,cortex-a15-pmu";
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + };
As these are SPIs, you should fill in the interrupt-affinity property
(see Documentation/devicetree/bindings/arm/pmu.txt). That'll avoid
potential problems with CPU renumbering, and prevent the kernel from
complaining at boot time.
Otherwise, this looks fine.
Thanks,
Mark.
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