[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20150616091857.GK3644@twins.programming.kicks-ass.net>
Date: Tue, 16 Jun 2015 11:18:57 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Vikas Shivappa <vikas.shivappa@...el.com>
Cc: Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel@...r.kernel.org, x86@...nel.org, hpa@...or.com,
tglx@...utronix.de, mingo@...nel.org,
Matt Fleming <matt.fleming@...el.com>,
"Juvva, Kanaka D" <kanaka.d.juvva@...el.com>,
"Williamson, Glenn P" <glenn.p.williamson@...el.com>,
"Auld, Will" <will.auld@...el.com>
Subject: Re: [PATCH 10/10] x86/intel_rdt: Intel haswell Cache Allocation
enumeration
On Mon, Jun 15, 2015 at 02:44:32PM -0700, Vikas Shivappa wrote:
> >Secondly, there's more HSW models:
> >
> > case 60: /* 22nm Haswell Core */
> > case 63: /* 22nm Haswell Server */
> > case 69: /* 22nm Haswell ULT */
> > case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
> >
> >Is this really only HSW server,
>
> Yes , this probe is only targeted at HSW servers as of now.
But do the others have it? What you're targeting this code for is
irrelevant, if those models have the hardware we should support them.
> or should they all be listed?
If they support it, yes. In any case, be explicit on which models have
the hardware. IIRC your current Changelog has the words 'certain SKUs'
in, which is as ambiguous as one can get.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists