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Date: Tue, 16 Jun 2015 16:25:11 +0100 From: Sifan Naeem <sifan.naeem@...tec.com> To: <broonie@...nel.org> CC: <linux-spi@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <abrestic@...omium.org>, Sifan Naeem <sifan.naeem@...tec.com> Subject: [PATCH] spi: img-spfi: Same Edge bit set to double supported transfer speed Same edge bit set in SPFI Control register to double the supported spfi clock speed. According to the TRM setting this bit increases the supported frequency from 1/8 to 1/4 of the Core clock frequency. Without this bit set the maximum speed would be 25MHz on Pistachio. Signed-off-by: Sifan Naeem <sifan.naeem@...tec.com> --- drivers/spi/spi-img-spfi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index 788e2b1..acce90a 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -40,6 +40,7 @@ #define SPFI_CONTROL_SOFT_RESET BIT(11) #define SPFI_CONTROL_SEND_DMA BIT(10) #define SPFI_CONTROL_GET_DMA BIT(9) +#define SPFI_CONTROL_SE BIT(8) #define SPFI_CONTROL_TMODE_SHIFT 5 #define SPFI_CONTROL_TMODE_MASK 0x7 #define SPFI_CONTROL_TMODE_SINGLE 0 @@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi, else if (xfer->tx_nbits == SPI_NBITS_QUAD && xfer->rx_nbits == SPI_NBITS_QUAD) val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; + val |= SPFI_CONTROL_SE; spfi_writel(spfi, val, SPFI_CONTROL); } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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