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Message-ID: <A0E307549471DA4DBAF2DE2DE6CBFB7E4961A865@hhmail02.hh.imgtec.org>
Date: Thu, 18 Jun 2015 12:52:11 +0000
From: Sifan Naeem <Sifan.Naeem@...tec.com>
To: "broonie@...nel.org" <broonie@...nel.org>
CC: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"abrestic@...omium.org" <abrestic@...omium.org>
Subject: RE: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported
transfer speed
Please ignore this patch. I have posted a new patch as a fix after the discussion with Jonas Gorski.
https://patchwork.kernel.org/patch/6636761/ spi: img-spfi: fix support for speeds up to 1/4th input clock
Thanks,
Sifan
> -----Original Message-----
> From: Sifan Naeem
> Sent: 17 June 2015 11:48
> To: broonie@...nel.org
> Cc: linux-spi@...r.kernel.org; linux-kernel@...r.kernel.org;
> abrestic@...omium.org; Sifan Naeem
> Subject: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported
> transfer speed
>
> Same edge bit set in SPFI Control register to double the supported spfi clock
> speed. Setting this bit increases the supported spfi frequency from 1/8 to 1/4
> of the core clock frequency.
>
> Without this bit set the maximum speed supported was 25MHz on Pistachio.
>
> Signed-off-by: Sifan Naeem <sifan.naeem@...tec.com>
> ---
> changes from v2: Gerrit Change-Id removed from commit message
> drivers/spi/spi-img-spfi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index
> 788e2b1..acce90a 100644
> --- a/drivers/spi/spi-img-spfi.c
> +++ b/drivers/spi/spi-img-spfi.c
> @@ -40,6 +40,7 @@
> #define SPFI_CONTROL_SOFT_RESET BIT(11)
> #define SPFI_CONTROL_SEND_DMA BIT(10)
> #define SPFI_CONTROL_GET_DMA BIT(9)
> +#define SPFI_CONTROL_SE BIT(8)
> #define SPFI_CONTROL_TMODE_SHIFT 5
> #define SPFI_CONTROL_TMODE_MASK 0x7
> #define SPFI_CONTROL_TMODE_SINGLE 0
> @@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master
> *master, struct spi_device *spi,
> else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
> xfer->rx_nbits == SPI_NBITS_QUAD)
> val |= SPFI_CONTROL_TMODE_QUAD <<
> SPFI_CONTROL_TMODE_SHIFT;
> + val |= SPFI_CONTROL_SE;
> spfi_writel(spfi, val, SPFI_CONTROL);
> }
>
> --
> 1.7.9.5
--
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