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Message-ID: <tip-4b36f1a4139c9284df74c0f5d7655603d67807df@git.kernel.org>
Date: Fri, 19 Jun 2015 10:58:01 -0700
From: tip-bot for Andi Kleen <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: luto@...capital.net, brgerst@...il.com, akpm@...ux-foundation.org,
peterz@...radead.org, tglx@...utronix.de, ak@...ux.intel.com,
bp@...en8.de, mingo@...nel.org, torvalds@...ux-foundation.org,
dvlasenk@...hat.com, oleg@...hat.com, hpa@...or.com,
linux-kernel@...r.kernel.org
Subject: [tip:perf/urgent] perf/x86: Add more Broadwell model numbers
Commit-ID: 4b36f1a4139c9284df74c0f5d7655603d67807df
Gitweb: http://git.kernel.org/tip/4b36f1a4139c9284df74c0f5d7655603d67807df
Author: Andi Kleen <ak@...ux.intel.com>
AuthorDate: Thu, 11 Jun 2015 13:52:22 -0700
Committer: Ingo Molnar <mingo@...nel.org>
CommitDate: Fri, 19 Jun 2015 09:38:46 +0200
perf/x86: Add more Broadwell model numbers
This patch adds additional model numbers for Broadwell to perf.
Support for Broadwell with Iris Pro (Intel Core i7-57xxC)
and support for Broadwell Server Xeon.
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Cc: Andy Lutomirski <luto@...capital.net>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Brian Gerst <brgerst@...il.com>
Cc: Denys Vlasenko <dvlasenk@...hat.com>
Cc: H. Peter Anvin <hpa@...or.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Oleg Nesterov <oleg@...hat.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/1434055942-28253-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index a1e35c9..afdd7c0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -3253,6 +3253,8 @@ __init int intel_pmu_init(void)
case 61: /* 14nm Broadwell Core-M */
case 86: /* 14nm Broadwell Xeon D */
+ case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
+ case 79: /* 14nm Broadwell Server */
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
--
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