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Message-ID: <CAErSpo7rE8yAS--L+aQmN-DqfL6uGxFBxD2WOPowoBsrvOZ7eg@mail.gmail.com>
Date:	Fri, 26 Jun 2015 09:26:21 -0500
From:	Bjorn Helgaas <bhelgaas@...gle.com>
To:	Duc Dang <dhdang@....com>
Cc:	Catalin Marinas <catalin.marinas@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Pawel Moll <pawel.moll@....com>,
	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Kumar Gala <galak@...eaurora.org>,
	Will Deacon <will.deacon@....com>,
	"David S. Miller" <davem@...emloft.net>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	linux-arm <linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Tanmay Inamdar <tinamdar@....com>, patches <patches@....com>
Subject: Re: [PATCH 1/1] pci: xgene: Enable huge outbound bar support

Hi Duc,

On Thu, Jun 25, 2015 at 8:05 PM, Duc Dang <dhdang@....com> wrote:
> X-Gene PCIe controllers support huge outbound BARs (with size upto
> 64GB). This patch configures additional 1 outbound BAR for X-Gene
> PCIe controllers with size larger than 4GB. This is required to
> support devices that request huge outbound memory (nVidia K40 as an
> example)

The PCI specs don't use the "outbound BAR" terminology.  I assume this
is what we normally call "windows" or "apertures" for MMIO access by
the CPU?  (The specs rarely use those terms either, but they're
commonly used in Linux, and the PCIe spec does mention them a couple
times.)

By "request huge outbound memory," I assume you simply mean the device
has a huge BAR, right?

Bjorn
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