linux-kernel - Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support

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Message-ID: <20150627144054.GW19530@localhost>
Date:	Sat, 27 Jun 2015 20:10:54 +0530
From:	Vinod Koul <vinod.koul@...el.com>
To:	Appana Durga Kedareswara Rao <appana.durga.rao@...inx.com>
Cc:	"dan.j.williams@...el.com" <dan.j.williams@...el.com>,
	Michal Simek <michals@...inx.com>,
	Soren Brinkmann <sorenb@...inx.com>,
	Anirudha Sarangi <anirudh@...inx.com>,
	Punnaiah Choudary Kalluri <punnaia@...inx.com>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Srikanth Thokala <sthokal@...inx.com>
Subject: Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine
 driver support

On Wed, Jun 24, 2015 at 05:12:13PM +0000, Appana Durga Kedareswara Rao wrote:
> > where is the hardware addr programmed? I can see you are using sg list
> > passed for porgramming one side of a transfer where is other side
> > programmed?
> 
> The actual programming happens in the start_transfer(I mean in issue_pending) API
> There are two modes
> 
> All the h/w addresses are configured in the start_transfer API.
> 
> In simple transfer Mode the below write triggers the transfer
> dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
>                                hw->control & XILINX_DMA_MAX_TRANS_LEN);
> 
> In SG Mode the below write triggers the transfer.
> dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, tail->phys);
> 
> There are two Channels MM2S (Memory to device) and S2MM (Device to Memory) channel.
> --> In MM2S case we need to configure the SOF (Start of frame) for the first BD and we need to set EOF(end of frame) for the last BD
> --> For S2MM case no need to configure SOF and EOF. Once we got the IOC interrupt will call mark the cookie as complete and will
> Call the user callback. There users checks for the data.
> 
> Please let me know if you are not clear.
No sorry am not...

I asked how the device address in configured. For both MM2S S2MM you are
using sg for memory address, where are you getting device adress, are you
assuming/hardcoding or getting somehow, if so how?

> > no dma_slave_config handler?
> No need of this callback earlier in the dma_slave_config we are doing terminate_all
> Now we have a separate API for that so no need to have this call back.

The question was on parameters

-- 
~Vinod
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