linux-kernel - Re: [Xen-devel] [PATCH v7 5/9] PCI: Add pci_iomap

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Message-ID: <1435362871.26815.24.camel@kernel.crashing.org>
Date:	Sat, 27 Jun 2015 09:54:31 +1000
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	"Luis R. Rodriguez" <mcgrof@...e.com>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Dave Airlie <airlied@...hat.com>,
	"Michael S. Tsirkin" <mst@...hat.com>,
	Andy Lutomirski <luto@...capital.net>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Suresh Siddha <sbsiddha@...il.com>,
	Ingo Molnar <mingo@...e.hu>,
	Antonino Daplas <adaplas@...il.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Roger Pau Monné <roger.pau@...rix.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Daniel Vetter <daniel.vetter@...ll.ch>,
	ville.syrjala@...ux.intel.com,
	"venkatesh.pallipadi@...el.com" <venkatesh.pallipadi@...el.com>,
	Jean-Christophe Plagniol-Villard <plagnioj@...osoft.com>,
	Tomi Valkeinen <tomi.valkeinen@...com>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	linux-fbdev <linux-fbdev@...r.kernel.org>,
	David Vrabel <david.vrabel@...rix.com>,
	Casey Leedom <leedom@...lsio.com>,
	Juergen Gross <jgross@...e.com>,
	Toshi Kani <toshi.kani@...com>,
	"xen-devel@...ts.xensource.com" <xen-devel@...ts.xensource.com>,
	Stefan Bader <stefan.bader@...onical.com>,
	Arnd Bergmann <arnd@...db.de>, Jan Beulich <jbeulich@...e.com>
Subject: Re: [Xen-devel] [PATCH v7 5/9] PCI: Add pci_iomap_wc() variants

On Fri, 2015-06-26 at 15:41 -0700, Luis R. Rodriguez wrote:

> > It wasn't nullified for the main user at the time, the fb. And I
> > mentioned an IB adapter or two for which the code had been hand
> tuned.
> 
> This still means there could be some affected drivers when used on
> powerpc, no?

Yes. In fact what about things like ARM who also have barriers in their
writel() ? Won't they also break WC ?

I'm trying to work with the architect and designers here to figure out
exactly where we stand and what we can do. As spelled out by our
architecture, things don't look great, because basically, we only have
attribute bit (garded) which when not set implies both WC and out of
order (& prefetch), and unclear barrier semantics in that case as well.

I *think* we might be able to settle with something along the lines of
"writel_relaxed() will allow combine on a WC mapping" but how I'm going
to get there is TBD.

It would be interesting to clarify the semantics of using the relaxed
accessors in combination with WC anyway. I wouldn't mind if the
definition involved also relaxing general ordering :-) It would
definitely make my life easier.

Cheers,
Ben.

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