linux-kernel - Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support

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Message-ID: <20150628144529.GZ19530@localhost>
Date:	Sun, 28 Jun 2015 20:15:29 +0530
From:	Vinod Koul <vinod.koul@...el.com>
To:	Nicolae Rosia <nicolae.rosia@...il.com>
Cc:	Appana Durga Kedareswara Rao <appana.durga.rao@...inx.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Srikanth Thokala <sthokal@...inx.com>,
	Michal Simek <michals@...inx.com>,
	Soren Brinkmann <sorenb@...inx.com>,
	Anirudha Sarangi <anirudh@...inx.com>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
	Punnaiah Choudary Kalluri <punnaia@...inx.com>,
	"dan.j.williams@...el.com" <dan.j.williams@...el.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine
 driver support

On Sat, Jun 27, 2015 at 05:44:38PM +0300, Nicolae Rosia wrote:
> On Sat, Jun 27, 2015 at 5:40 PM, Vinod Koul <vinod.koul@...el.com> wrote:
> [...]
> >> Please let me know if you are not clear.
> > No sorry am not...
> >
> > I asked how the device address in configured. For both MM2S S2MM you are
> > using sg for memory address, where are you getting device adress, are you
> > assuming/hardcoding or getting somehow, if so how?
> As the name says, one end is memory (MM) and the other end is an AXI4
> Stream Bus (S) which has no concept of memory address.
> So yes, it is hardcoded at design time.
So where does the data go at the end of stream bus, who configures that?
Shouldnt all this be at least documented...

-- 
~Vinod
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