linux-kernel - RE: perf: fuzzer triggered warning in intel_pmu_drain_pebs

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Message-ID: <37D7C6CF3E00A74B8858931C1DB2F07701886203@SHSMSX103.ccr.corp.intel.com>
Date:	Mon, 6 Jul 2015 13:47:42 +0000
From:	"Liang, Kan" <kan.liang@...el.com>
To:	Peter Zijlstra <peterz@...radead.org>,
	"Vince Weaver (vincent.weaver@...ne.edu)" <vincent.weaver@...ne.edu>
CC:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	"Stephane Eranian" <eranian@...il.com>
Subject: RE: perf: fuzzer triggered warning in intel_pmu_drain_pebs_nhm()


> On Fri, Jul 03, 2015 at 08:08:27PM +0000, Liang, Kan wrote:
> > If we cleared the last bit, we not only drain the buffer but also
> > decrease the event->ctx->pmu, which is used to flush the PEBS buffer
> > during context switches.
> > We need to disable cpuc->pebs_enabled before changing
> > event->ctx->pmu as below.
> >
> 
> Indeed, mind sending a proper patch so I can press 'A' on it?

Sure, I will do that.
But I didn't verify the patch, since I cannot reproduce the issue.

Vince, would you mind testing the patch?
If the issue is gone, I will send a proper patch then.

Thanks,
Kan

> 
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> > b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> > index 71fc402..76285c1 100644
> > --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> > @@ -754,6 +754,11 @@ void intel_pmu_pebs_disable(struct perf_event
> > *event)
> >         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> >         struct hw_perf_event *hwc = &event->hw;
> >         struct debug_store *ds = cpuc->ds;
> > +       bool large_pebs = ds->pebs_interrupt_threshold >
> > +                         ds->pebs_buffer_base +
> > + x86_pmu.pebs_record_size;
> > +
> > +       if (large_pebs)
> > +               intel_pmu_drain_pebs_buffer();
> >
> >         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
> >
> > @@ -762,12 +767,8 @@ void intel_pmu_pebs_disable(struct perf_event
> > *event)
> >         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
> >                 cpuc->pebs_enabled &= ~(1ULL << 63);
> >
> > -       if (ds->pebs_interrupt_threshold >
> > -           ds->pebs_buffer_base + x86_pmu.pebs_record_size) {
> > -               intel_pmu_drain_pebs_buffer();
> > -               if (!pebs_is_enabled(cpuc))
> > -                       perf_sched_cb_dec(event->ctx->pmu);
> > -       }
> > +       if (large_pebs && !pebs_is_enabled(cpuc))
> > +               perf_sched_cb_dec(event->ctx->pmu);
> >
> >         if (cpuc->enabled)
> >                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
> >
> >
> >
> > Thanks,
> > Kan
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