linux-kernel - Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface

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Message-ID: <alpine.DEB.2.11.1507061747100.3916@nanos>
Date:	Mon, 6 Jul 2015 17:47:40 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Ingo Molnar <mingo@...nel.org>
cc:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	x86@...nel.org, Aubrey Li <aubrey.li@...ux.intel.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
	"Kumar P, Mahesh" <mahesh.kumar.p@...el.com>,
	linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org
Subject: Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface

On Mon, 6 Jul 2015, Ingo Molnar wrote:
 
> * Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote:
> 
> > The patch adds CHT PMC interface. This exposes all the South IP device power
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > not aligned. This is fixed by splitting a common mapping on per register basis.
> > 
> > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@...el.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> 
> That's a weird signoff sequence. I changed it to:
> 
>  Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
>  Acked-by: Kumar P Mahesh <mahesh.kumar.p@...el.com>

It might lack a From: Kumar ... 
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