linux-kernel - Re: [tip:x86/platform] x86/platform/intel/pmc

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Message-ID: <20150706190917.GK3644@twins.programming.kicks-ass.net>
Date:	Mon, 6 Jul 2015 21:09:17 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	linux-kernel@...r.kernel.org, torvalds@...ux-foundation.org,
	mahesh.kumar.p@...el.com, tglx@...utronix.de,
	rafael.j.wysocki@...el.com, andriy.shevchenko@...ux.intel.com,
	hpa@...or.com, mingo@...nel.org, aubrey.li@...ux.intel.com
Cc:	linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail
 PMC interface

On Mon, Jul 06, 2015 at 09:35:33AM -0700, tip-bot for Kumar P Mahesh wrote:
> Commit-ID:  daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> Gitweb:     http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> Author:     Kumar P Mahesh <mahesh.kumar.p@...el.com>
> AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
> Committer:  Ingo Molnar <mingo@...nel.org>
> CommitDate: Mon, 6 Jul 2015 17:50:59 +0200
> 
> x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
> 
> The patch adds CHT PMC interface. This exposes all the South IP
> device power states and S0ix states for CHT. The bit map of
> FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
> D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
> This is fixed by splitting a common mapping on per register basis.

TLA collision.. I thought this was about performance monitor counters :/
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