linux-kernel - [PATCH 0/2] Add MT8173 MMPLL change rate support

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Message-ID: <1436344666-25645-1-git-send-email-jamesjj.liao@mediatek.com>
Date:	Wed, 8 Jul 2015 16:37:44 +0800
From:	James Liao <jamesjj.liao@...iatek.com>
To:	Matthias Brugger <matthias.bgg@...il.com>,
	Mike Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Heiko Stubner <heiko@...ech.de>
CC:	<srv_heupstream@...iatek.com>, Daniel Kurtz <djkurtz@...omium.org>,
	Ricky Liang <jcliang@...omium.org>,
	Rob Herring <robh+dt@...nel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	<devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	<linux-mediatek@...ts.infradead.org>
Subject: [PATCH 0/2] Add MT8173 MMPLL change rate support

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
3. Write postdiv and pcw settings at the same time.

James Liao (2):
  clk: mediatek: Fix PLL registers setting flow
  clk: mediatek: Add MT8173 MMPLL change rate support

 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
 3 files changed, 54 insertions(+), 15 deletions(-)

--
1.8.1.1.dirty

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