linux-kernel - Re: [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

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Message-ID: <79801022.IfOq8aeLEc@diego>
Date:	Wed, 08 Jul 2015 10:58:55 +0200
From:	Heiko Stübner <heiko@...ech.de>
To:	James Liao <jamesjj.liao@...iatek.com>
Cc:	Matthias Brugger <matthias.bgg@...il.com>,
	Mike Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	srv_heupstream@...iatek.com, Daniel Kurtz <djkurtz@...omium.org>,
	Ricky Liang <jcliang@...omium.org>,
	Rob Herring <robh+dt@...nel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

Am Mittwoch, 8. Juli 2015, 16:37:45 schrieb James Liao:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
> 
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
> 
> Signed-off-by: James Liao <jamesjj.liao@...iatek.com>

Reviewed-by: Heiko Stuebner <heiko@...ech.de>
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