linux-kernel - Re: [PATCH RESEND 2/6] drm/exynos/mixer: fix interrupt clearing

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Date:	Thu, 09 Jul 2015 16:47:15 +0900
From:	Joonyoung Shim <jy0922.shim@...sung.com>
To:	Andrzej Hajda <a.hajda@...sung.com>, inki.dae@...sung.com
Cc:	b.zolnierkie@...sung.com, linux-kernel@...r.kernel.org,
	dri-devel@...ts.freedesktop.org,
	Kyungmin Park <kyungmin.park@...sung.com>,
	Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: [PATCH RESEND 2/6] drm/exynos/mixer: fix interrupt clearing

On 07/09/2015 03:25 PM, Andrzej Hajda wrote:
> The driver used incorrect flags to clear interrupt status.
> The patch fixes it.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@...sung.com>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index cae98db..0686484 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -718,6 +718,9 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
>  
>  	/* handling VSYNC */
>  	if (val & MXR_INT_STATUS_VSYNC) {
> +		/* vsync interrupt use different bit for read and clear */
> +		val |= MXR_INT_CLEAR_VSYNC;

MXR_INT_STATUS_VSYNC bit of MXR_INT_STATUS register is read-only, so it
needs to be clear MXR_INT_STATUS_VSYNC bit of val.

> +
>  		/* interlace scan need to check shadow register */
>  		if (ctx->interlace) {
>  			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
> @@ -743,11 +746,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
>  
>  out:
>  	/* clear interrupts */
> -	if (~val & MXR_INT_EN_VSYNC) {
> -		/* vsync interrupt use different bit for read and clear */
> -		val &= ~MXR_INT_EN_VSYNC;
> -		val |= MXR_INT_CLEAR_VSYNC;
> -	}
>  	mixer_reg_write(res, MXR_INT_STATUS, val);
>  
>  	spin_unlock(&res->reg_slock);
> 

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