linux-kernel - Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

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Message-ID: <CAHp75Vd7r-2+WASvoeCT_NO8JEtsxYPH5fXBKe=VpYA2LDv5tQ@mail.gmail.com>
Date:	Thu, 9 Jul 2015 23:54:07 +0300
From:	Andy Shevchenko <andy.shevchenko@...il.com>
To:	Dinh Nguyen <dinguyen@...nsource.altera.com>
Cc:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	Tero Kristo <t-kristo@...com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Russell King <linux@....linux.org.uk>
Subject: Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

On Thu, Jul 9, 2015 at 10:50 PM, Dinh Nguyen
<dinguyen@...nsource.altera.com> wrote:
> Hi Andy,
>
> On 07/09/2015 11:43 AM, Andy Shevchenko wrote:
>> Convert the code to use GENMASK() helper instead of div_mask() macro.
>>
>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
>> ---
>>  drivers/clk/socfpga/clk-gate.c   | 2 +-
>>  drivers/clk/socfpga/clk-periph.c | 2 +-
>>  drivers/clk/socfpga/clk.h        | 1 -
>>  3 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
>> index dd3a78c..d61052e 100644
>> --- a/drivers/clk/socfpga/clk-gate.c
>> +++ b/drivers/clk/socfpga/clk-gate.c
>> @@ -110,7 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>>               div = socfpgaclk->fixed_div;
>>       else if (socfpgaclk->div_reg) {
>>               val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
>> -             val &= div_mask(socfpgaclk->width);
>> +             val &= GENMASK(socfpgaclk->width - 1, 0);
>>               /* Check for GPIO_DB_CLK by its offset */
>>               if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
>>                       div = val + 1;
>> diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
>> index 46531c3..fc410a4 100644
>> --- a/drivers/clk/socfpga/clk-periph.c
>> +++ b/drivers/clk/socfpga/clk-periph.c
>> @@ -36,7 +36,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
>>       } else {
>>               if (socfpgaclk->div_reg) {
>>                       val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
>> -                     val &= div_mask(socfpgaclk->width);
>> +                     val &= GENMASK(socfpgaclk->width - 1, 0);
>>                       parent_rate /= (val + 1);
>>               }
>>               div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
>> diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
>> index d291f60..5278156 100644
>> --- a/drivers/clk/socfpga/clk.h
>> +++ b/drivers/clk/socfpga/clk.h
>> @@ -27,7 +27,6 @@
>>  #define CLKMGR_PERPLL_SRC    0xAC
>>
>>  #define SOCFPGA_MAX_PARENTS          3
>> -#define div_mask(width) ((1 << (width)) - 1)
>>
>>  extern void __iomem *clk_mgr_base_addr;
>>
>>
>
> Thanks for doing this, but this patch did not apply for me on v4.2-rc1.
> Also, there are now socfpga/clk-gate-a10.c and socfpga/clk-periph-a10.c
> that would also need to use GENMASK. Can you please rebase and resend?

Ah, usually I'm using linux-next, seems I have to rebase on top of clk
tree. I hope changes you mentioned are there.


-- 
With Best Regards,
Andy Shevchenko
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