linux-kernel - Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller

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Message-ID: <20150713145907.GF11162@sirena.org.uk>
Date:	Mon, 13 Jul 2015 15:59:07 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Mike Looijmans <mike.looijmans@...ic.nl>
Cc:	Ranjit Waghmode <ranjit.waghmode@...inx.com>,
	michal.simek@...inx.com, soren.brinkmann@...inx.com,
	dwmw2@...radead.org, computersforpeace@...il.com, zajec5@...il.com,
	marex@...x.de, shijie.huang@...el.com, juhosg@...nwrt.org,
	ben@...adent.org.uk, harinik@...inx.com,
	linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
	linux-mtd@...ts.infradead.org, punnaia@...inx.com,
	ran27jit@...il.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in
 Zynq MPSoC GQSPI controller

On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote:
> On 09-07-15 14:44, Ranjit Waghmode wrote:

> >ZynqMP GQSPI controller supports stacked mode with following functionalities:
> >1) The Generic Quad-SPI controller also supports two SPI flash memories
> >    in a shared bus arrangement to reduce IO pin count.
> >2) Separate chip select lines
> >3) Shared I/O lines
> >4) This mode is targeted for increasing the flash memory and no performance
> >    improvement when compared with single.

> One could also model the stacked mode as having two distinct flash chips
> with separate chip selects and shared lines.

Well, quite.  I'm confused about how the above differs from a just a SPI
controller with two chip selects which is perfectly standard.

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