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Message-ID: <55A66486.9000609@ti.com>
Date: Wed, 15 Jul 2015 16:47:50 +0300
From: Roger Quadros <rogerq@...com>
To: Tony Lindgren <tony@...mide.com>,
Kishon Vijay Abraham I <kishon@...com>
CC: <nm@...com>, <nsekhar@...com>, <balbi@...com>,
<grygorii.strashko@...com>, <linux-kernel@...r.kernel.org>,
<linux-omap@...r.kernel.org>, Tero Kristo <t-kristo@...com>
Subject: Re: [PATCH v2 3/3] ARM: dts: dra7: Add syscon-pllreset syscon to
SATA PHY
Hi,
On 15/07/15 15:07, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kishon@...com> [150715 04:24]:
>> Hi Roger,
>>
>> On Tuesday 02 June 2015 02:40 PM, Roger Quadros wrote:
>>> This register is required to be passed to the SATA PHY driver
>>> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
>>>
>>> Signed-off-by: Roger Quadros <rogerq@...com>
>>> Signed-off-by: Sekhar Nori <nsekhar@...com>
>>> ---
>>> arch/arm/boot/dts/dra7.dtsi | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index f03a091..260f300 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -1135,6 +1135,7 @@
>>> ctrl-module = <&omap_control_sata>;
>>> clocks = <&sys_clkin1>, <&sata_ref_clk>;
>>> clock-names = "sysclk", "refclk";
>>> + syscon-pllreset = <&dra7_ctrl_core 0x3fc>;
>>
>> I think all users of syscon should be made child node of scm_conf. Tony and
>> Tero, is that right?
It can't be child of scm_conf as the address is outside it's range.
Looks like I have to add a new child to scm node that maps beyond
the dra7_pmx_core padconf address range.
>>
>> If so, then we might have to modify the driver too.
>
> Yeah there should not be much need to use syscon outside scm_conf
> area and for I2C devices. If there's some other misc register area
> in dra7 in addition to scm_conf then it might make sense to use it.
>
> But in general, for the SCM registers, just a normal loadable kernel
> driver module doing of_ioremap on a dedicated range of registers is
> always a better option :)
>
Lets take for example this register CTRL_CORE_SMA_SW_0.
It has the SATA PLL_SOFT_RESET bit, EMIF1/2 gating control bits
and ISOLATE bit.
I don't see this fitting in any driver except the syscon approach.
cheers,
-roger
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