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Message-ID: <20150715160146.GS11162@sirena.org.uk>
Date:	Wed, 15 Jul 2015 17:01:46 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Ranjit Abhimanyu Waghmode <ranjit.waghmode@...inx.com>
Cc:	Michal Simek <michals@...inx.com>,
	Soren Brinkmann <sorenb@...inx.com>,
	"dwmw2@...radead.org" <dwmw2@...radead.org>,
	"computersforpeace@...il.com" <computersforpeace@...il.com>,
	"zajec5@...il.com" <zajec5@...il.com>,
	"marex@...x.de" <marex@...x.de>,
	"shijie.huang@...el.com" <shijie.huang@...el.com>,
	"juhosg@...nwrt.org" <juhosg@...nwrt.org>,
	"ben@...adent.org.uk" <ben@...adent.org.uk>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Harini Katakam <harinik@...inx.com>,
	Punnaiah Choudary Kalluri <punnaia@...inx.com>,
	"ran27jit@...il.com" <ran27jit@...il.com>
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in
 Zynq MPSoC GQSPI controller

On Wed, Jul 15, 2015 at 02:12:54PM +0000, Ranjit Abhimanyu Waghmode wrote:

> > > What is stacked mode?
> > > ---------------------
> > > ZynqMP GQSPI controller supports stacked mode with following
> > functionalities:
> > > 1) The Generic Quad-SPI controller also supports two SPI flash memories
> > >    in a shared bus arrangement to reduce IO pin count.
> > > 2) Separate chip select lines
> > > 3) Shared I/O lines
> > > 4) This mode is targeted for increasing the flash memory and no performance
> > >    improvement when compared with single.

> > This is just a normal SPI controller from a SPI point of view.

> How can we really represent the stacked mode in current configuration?

In the same way as any other controller with two chip selects...  there
are quite a few other drivers that provide examples of this, you should
look for one that has hardware control similar to yours.

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