linux-kernel - Re: [PATCH 4/5] irqchip: gic-v3: Add gic_get_irq_domain() to get the irqdomain of the GIC.

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Message-ID: <55A75F8B.3080009@arm.com>
Date:	Thu, 16 Jul 2015 08:38:51 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	David Daney <ddaney@...iumnetworks.com>
CC:	David Daney <ddaney.cavm@...il.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Catalin Marinas <Catalin.Marinas@....com>,
	Will Deacon <Will.Deacon@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Robert Richter <rrichter@...ium.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	David Daney <david.daney@...ium.com>
Subject: Re: [PATCH 4/5] irqchip: gic-v3: Add gic_get_irq_domain() to get
 the irqdomain of the GIC.

On 15/07/15 19:57, David Daney wrote:
> On 07/15/2015 10:12 AM, Marc Zyngier wrote:
>> On 15/07/15 17:54, David Daney wrote:
>>> From: David Daney <david.daney@...ium.com>
>>>
>>> Needed to map SPI interrupt sources.
>>>
>>> Signed-off-by: David Daney <david.daney@...ium.com>
>>> ---
>>>   drivers/irqchip/irq-gic-v3.c       | 5 +++++
>>>   include/linux/irqchip/arm-gic-v3.h | 1 +
>>>   2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>>> index c52f7ba..0019fed 100644
>>> --- a/drivers/irqchip/irq-gic-v3.c
>>> +++ b/drivers/irqchip/irq-gic-v3.c
>>> @@ -58,6 +58,11 @@ static struct gic_chip_data gic_data __read_mostly;
>>>   /* Our default, arbitrary priority value. Linux only uses one anyway. */
>>>   #define DEFAULT_PMR_VALUE	0xf0
>>>
>>> +struct irq_domain *gic_get_irq_domain(void)
>>> +{
>>> +	return gic_data.domain;
>>> +}
>>> +
>>>   static inline unsigned int gic_irq(struct irq_data *d)
>>>   {
>>>   	return d->hwirq;
>>> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
>>> index 18e3757..5992224 100644
>>> --- a/include/linux/irqchip/arm-gic-v3.h
>>> +++ b/include/linux/irqchip/arm-gic-v3.h
>>> @@ -391,6 +391,7 @@ int its_init(struct device_node *node, struct rdists *rdists,
>>>
>>>   typedef u32 (*its_pci_requester_id_t)(struct pci_dev *, u16);
>>>   void set_its_pci_requester_id(its_pci_requester_id_t fn);
>>> +struct irq_domain *gic_get_irq_domain(void);
>>>   #endif
>>>
>>>   #endif
>>>
>>
>> Hmmmffff... You need the domain for SPIs??
>>
>> What is wrong with putting these interrupts in your device tree?
>>
> 
> There is no device tree node for ECAM based "PCIe" devices, they are 
> discovered in the PCI bus scan, yet they still need to use SPI interrupts.

What is different between these and the normal legacy interrupts that
are normally expressed in the RC node using an interrupt map? Sorry if
I'm only showing my ignorance here, but I'd like to understand the exact
nature of the problem.

> We need a way to be able to map these.

However you're going to map them, it will not be by just blindly
exporting random irqdomains from an unsuspecting interrupt controller.

Patch 5 has established that you're using "virtual wire" SPIs, so we
need to work on exposing that with the normal kernel abstraction, and
not by messing with the internals of the GIC.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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