linux-kernel - Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller

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Message-ID: <55A770E2.2040300@arm.com>
Date:	Thu, 16 Jul 2015 09:52:50 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	"majun (F)" <majun258@...wei.com>,
	Thomas Gleixner <tglx@...utronix.de>
CC:	Catalin Marinas <Catalin.Marinas@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Will Deacon <Will.Deacon@....com>,
	Mark Rutland <Mark.Rutland@....com>,
	"jason@...edaemon.net" <jason@...edaemon.net>,
	"lizefan@...wei.com" <lizefan@...wei.com>,
	"huxinwei@...wei.com" <huxinwei@...wei.com>,
	"dingtianhong@...wei.com" <dingtianhong@...wei.com>,
	"zhaojunhua@...ilicon.com" <zhaojunhua@...ilicon.com>,
	"liguozhu@...ilicon.com" <liguozhu@...ilicon.com>,
	"xuwei5@...ilicon.com" <xuwei5@...ilicon.com>,
	"wei.chenwei@...ilicon.com" <wei.chenwei@...ilicon.com>,
	"guohanjun@...wei.com" <guohanjun@...wei.com>,
	"wuyun.wu@...wei.com" <wuyun.wu@...wei.com>,
	"guodong.xu@...aro.org" <guodong.xu@...aro.org>,
	"haojian.zhuang@...aro.org" <haojian.zhuang@...aro.org>,
	"zhangfei.gao@...aro.org" <zhangfei.gao@...aro.org>,
	"usman.ahmad@...aro.org" <usman.ahmad@...aro.org>
Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen
 interrupt controller

On 16/07/15 09:35, majun (F) wrote:
> 
> 
> 在 2015/7/8 23:16, Marc Zyngier 写道:
>> On 08/07/15 05:21, majun (F) wrote:
>>> Hi Thomas:
>>>
> [...]
>>>>> +
>>>>> +	nid = GET_NODE_NUM(d->hwirq);
>>>>> +	ret = get_mbigen_node_type(nid);
>>>>> +	if (ret)
>>>>> +		return 0;
>>>>
>>>> Care to explain what this does? It seems for some nodes you cannot
>>>> write the msi message. So how is that supposed to work? How is that
>>>> interrupt controlled (mask/unmask ...) ?
>>>>
>>> This function is used to write irq event id into vector register.Depends on
>>> hardware design, write operation is permitted in some mbigen node(nid=0,5,and >7),
>>> For other mbigen node, this register is read only.
>>
>> So how do you expect this to work? You cannot program the event
>> generated by the mbigen, and the ITS has an ITT that probably doesn't
>> match your HW.
>>
>> Best case, the interrupt is simply dropped, worse case you end up in an
>> interrupt storm because you can't figure out which device is screaming.
>>
>> I'm a bit puzzled.
> 
> For interrupts connect to mbigen , the interrupt trigger type, device id and
> event id value are encoded in mbigen chip already.
> 
> There are two types of mbigen node within a mbigen chip.
> Type1: event id valud can't be programmed.
> Type2: event id value can be programmed.
> 
> For example: An device with 5 interrupts connected to Mbigen node
> type 1.The default event id vlaue encoded in mbigen chip for these 5 interrupt
> is from 0 to 4.
> 
> Because the event id value can't be programmed, we need to define all of
> 5 interrupts in dts file so that these 5 interrupt has

You can define what you want in the device tree, the ITS doesn't care!
Nothing in the ITS code parses this property, and there is absolutely
zero chance that the even the ITS has allocated will actually match what
you expect.

The ITS *relies* on the principle that the evenID can be programmed,
just like any MSI controller relies on the device to be programmed with
whatever payload has been provided. If all of a sudden we have to
support HW that has its own view of the payload, what you have here will
simply not work.

	M.
-- 
Jazz is not dead. It just smells funny...
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