linux-kernel - Re: [PATCH v2 1/6] locking/pvqspinlock: Unconditional PV kick with _Q_SLOW

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Message-ID: <20150716151006.GH26390@arm.com>
Date:	Thu, 16 Jul 2015 16:10:06 +0100
From:	Will Deacon <will.deacon@....com>
To:	Waiman Long <waiman.long@...com>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"H. Peter Anvin" <hpa@...or.com>,
	"x86@...nel.org" <x86@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Scott J Norton <scott.norton@...com>,
	Douglas Hatch <doug.hatch@...com>,
	Davidlohr Bueso <dave@...olabs.net>
Subject: Re: [PATCH v2 1/6] locking/pvqspinlock: Unconditional PV kick with
 _Q_SLOW_VAL

On Thu, Jul 16, 2015 at 04:04:30PM +0100, Waiman Long wrote:
> On 07/16/2015 10:07 AM, Waiman Long wrote:
> > On 07/16/2015 01:42 AM, Peter Zijlstra wrote:
> >> On Wed, Jul 15, 2015 at 08:18:23PM -0400, Waiman Long wrote:
> >>> On 07/15/2015 05:10 AM, Peter Zijlstra wrote:
> >>>>       /*
> >>>> +     * A failed cmpxchg doesn't provide any memory-ordering 
> >>>> guarantees,
> >>>> +     * so we need a barrier to order the read of the node data in
> >>>> +     * pv_unhash *after* we've read the lock being _Q_SLOW_VAL.
> >>>> +     *
> >>>> +     * Matches the cmpxchg() in pv_wait_head() setting _Q_SLOW_VAL.
> >>>> +     */
> >>>> +    smp_rmb();
> >>> According to memory_barriers.txt, cmpxchg() is a full memory 
> >>> barrier. It
> >>> didn't say a failed cmpxchg will lose its memory guarantee. So is the
> >>> documentation right?
> >> The documentation is not entirely clear on this; but there are hints
> >> that this is so.
> >>
> >>> Or is that true for some architectures? I think it is
> >>> not true for x86.
> >> On x86 LOCK CMPXCHG is always a sync point, but yes there are archs for
> >> which a failed cmpxchg does _NOT_ provide any barrier semantics.
> >>
> >> The reason I started looking was because Will made Argh64 one of those.
> >
> > That is what I suspected. In that case, I am fine with the patch as 
> > smp_rmb() is an nop in x86 anyway.
> >
> > Acked-by:  Waiman Long <Waiman.Long@...com>
> >
> > BTW, I think we also need to update the documentation to make it clear 
> > that a failed cmpxchg() or atomic_cmpxchg() may not be a full memory 
> > barrier as most people may not be aware of that.
> >

I already have a small patch for the Documentation (see below -- Peter,
you can pick this up too if you like).

> I suspect that there may be other places in the kernel that have similar 
> problem. An alternative will be to strengthen cmpxchg() in architectures 
> like arm64 to act as full memory barrier no matter the result and 
> defined relaxed version with no such guarantee.

Could do, but I don't think the ordering requirements are needed in the
vast majority of cases (as in, this case was the only one we could find)
and it gets really muddy when you want to define the semantics of something
like a failed cmpxchg_release.

Will

--->8

commit b2fdae71bdb621f62450076af4126cd8bca22918
Author: Will Deacon <will.deacon@....com>
Date:   Mon Jul 13 12:27:30 2015 +0100

    documentation: Clarify failed cmpxchg memory ordering semantics
    
    A failed cmpxchg does not provide any memory ordering guarantees, a
    property that is used to optimise the cmpxchg implementations on Alpha,
    PowerPC and arm64.
    
    This patch updates atomic_ops.txt and memory-barriers.txt to reflect
    this.
    
    Cc: Peter Zijlstra <peterz@...radead.org>
    Signed-off-by: Will Deacon <will.deacon@....com>

diff --git a/Documentation/atomic_ops.txt b/Documentation/atomic_ops.txt
index dab6da3382d9..b19fc34efdb1 100644
--- a/Documentation/atomic_ops.txt
+++ b/Documentation/atomic_ops.txt
@@ -266,7 +266,9 @@ with the given old and new values. Like all atomic_xxx operations,
 atomic_cmpxchg will only satisfy its atomicity semantics as long as all
 other accesses of *v are performed through atomic_xxx operations.
 
-atomic_cmpxchg must provide explicit memory barriers around the operation.
+atomic_cmpxchg must provide explicit memory barriers around the operation,
+although if the comparison fails then no memory ordering guarantees are
+required.
 
 The semantics for atomic_cmpxchg are the same as those defined for 'cas'
 below.
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 13feb697271f..18fc860df1be 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -2383,9 +2383,7 @@ about the state (old or new) implies an SMP-conditional general memory barrier
 explicit lock operations, described later).  These include:
 
 	xchg();
-	cmpxchg();
 	atomic_xchg();			atomic_long_xchg();
-	atomic_cmpxchg();		atomic_long_cmpxchg();
 	atomic_inc_return();		atomic_long_inc_return();
 	atomic_dec_return();		atomic_long_dec_return();
 	atomic_add_return();		atomic_long_add_return();
@@ -2398,7 +2396,9 @@ explicit lock operations, described later).  These include:
 	test_and_clear_bit();
 	test_and_change_bit();
 
-	/* when succeeds (returns 1) */
+	/* when succeeds */
+	cmpxchg();
+	atomic_cmpxchg();		atomic_long_cmpxchg();
 	atomic_add_unless();		atomic_long_add_unless();
 
 These are used for such things as implementing ACQUIRE-class and RELEASE-class
--
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