linux-kernel - Re: [PATCH 0/9] Intel core misc PMUs support

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Message-ID: <20150717113936.GA5396@gmail.com>
Date:	Fri, 17 Jul 2015 13:39:36 +0200
From:	Ingo Molnar <mingo@...nel.org>
To:	kan.liang@...el.com
Cc:	a.p.zijlstra@...llo.nl, mingo@...hat.com, acme@...nel.org,
	eranian@...gle.com, ak@...ux.intel.com, mark.rutland@....com,
	adrian.hunter@...el.com, dsahern@...il.com, jolsa@...nel.org,
	namhyung@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/9] Intel core misc PMUs support


* kan.liang@...el.com <kan.liang@...el.com> wrote:

> From: Kan Liang <kan.liang@...el.com>
> 
> This patchkit intends to support Intel core misc PMUs. There are miscellaneous 
> free running (read-only) counters in core. Some new PMUs called core misc PMUs 
> are composed to include these counters. The counters include TSC, IA32_APERF, 
> IA32_MPERF, IA32_PPERF, SMI_COUNT, CORE_C*_RESIDENCY and PKG_C*_RESIDENCY. There 
> could be more in future platform.

Could you please do something like:

  s/perf_event_intel_core_misc.c/perf_event_x86/

and in general propagate it to a core perf x86 position?

This feature is not Intel specific per se, although the initial MSRs you are 
supporting are Intel specific (and that is fine).

Thanks,

	Ingo
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