linux-kernel - Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support

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Date:	Fri, 17 Jul 2015 10:58:02 -0700
From:	Andy Lutomirski <luto@...capital.net>
To:	"Liang, Kan" <kan.liang@...el.com>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	Mark Rutland <mark.rutland@....com>,
	"mingo@...hat.com" <mingo@...hat.com>,
	"acme@...nel.org" <acme@...nel.org>,
	"eranian@...gle.com" <eranian@...gle.com>,
	"ak@...ux.intel.com" <ak@...ux.intel.com>,
	"Hunter, Adrian" <adrian.hunter@...el.com>,
	"dsahern@...il.com" <dsahern@...il.com>,
	"jolsa@...nel.org" <jolsa@...nel.org>,
	"namhyung@...nel.org" <namhyung@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"luto@...nel.org" <luto@...nel.org>
Subject: Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support

On Fri, Jul 17, 2015 at 10:52 AM, Liang, Kan <kan.liang@...el.com> wrote:
>
>
>>
>> On Fri, Jul 17, 2015 at 8:35 AM, Liang, Kan <kan.liang@...el.com> wrote:
>> >
>> >
>> >> On Fri, Jul 17, 2015 at 03:46:29PM +0200, Peter Zijlstra wrote:
>> >> > On Fri, Jul 17, 2015 at 01:11:41PM +0100, Mark Rutland wrote:
>> >> > > > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
>> >> > > > b/arch/x86/kernel/cpu/perf_event_intel.c
>> >> > > > index b9826a9..651a86d 100644
>> >> > > > --- a/arch/x86/kernel/cpu/perf_event_intel.c
>> >> > > > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>> >> > > > @@ -1586,6 +1586,8 @@ static int intel_pmu_handle_irq(struct
>> >> pt_regs *regs)
>> >> > > >         if (!x86_pmu.late_ack)
>> >> > > >                 apic_write(APIC_LVTPC, APIC_DM_NMI);
>> >> > > >         __intel_pmu_disable_all();
>> >> > > > +       if (cpuc->core_misc_active_mask)
>> >> > > > +               intel_core_misc_pmu_disable();
>> >> > >
>> >> > > Huh? Free running counters have nothing to do with the PMU
>> >> > > interrupt; there's nothing they can do to trigger it. This feels very
>> hacky.
>> >> > >
>> >> > > If this is necessary, surely it should live in __intel_pmu_disable_all?
>> >> > >
>> >> > > [...]
>> >> >
>> >> > Yeah this is crazy. It should not live in the regular PMU at all,
>> >> > not be Intel specific.
>> >>
>> >>
>> lkml.kernel.org/r/2c37309d20afadf88ad4a82cf0ce02b9152801e2.143025615
>> >> 4.git.luto@...nel.org
>> >>
>> >> That does the right thing for free running MSRs.
>> >>
>> >> Take it and expand.
>> >
>> > The first patch did the similar thing as the link you shared with.
>> > Here is the first patch.
>> > https://lkml.org/lkml/2015/7/16/953
>> >
>> > This patch is expend the per-core core_misc PMU based on the first
>> patch.
>> > I implemented this patch is because that one of the biggest concern
>> > from upstream for mix PMU group is that it breaks group semantics.
>> > When one PMU is stop, the other PMU is still running.
>> > So I introduce the enable/disable function. Other PMUs can discard the
>> > counter value for core_misc event when they are stop or in irq.
>> >
>> > If you think it should not live in the regular PMU, I can just remove the
>> codes.
>> > We just keep core_misc event running and no harm in it.
>>
>> I know very little about perf pmu organization, but I think that AMD
>> supports APERF and MPERF, too, so it may make sense to have that thing
>> live outside a file with "intel" in the name.
>>
>> Also, should the driver detect those using the cpuid bit?
>>
>
> Hi Andy,
>
> Yes, it detects the cpuid to determine which counters are available.
> If we want to implement a common file for both Intel and AMD,
> we can also check cupid.06h.ecx[bit 0] for a/mperf availability on Intel
> platform.
>
> Do you have a V2 patch already? I'm asking is because you once
> mentioned it... :)

No, and I also don't have PPERF hardware, etc, so there's not really
much I can do.  Feel free to do whatever you like with my v1.

--Andy
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