linux-kernel - Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake

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Message-ID: <CABPqkBSotpuiithZ4MQ7N4=Sawsrc5DSH+Den6oBQn1kB_fNDg@mail.gmail.com>
Date:	Fri, 17 Jul 2015 13:41:04 -0700
From:	Stephane Eranian <eranian@...gle.com>
To:	Andi Kleen <ak@...ux.intel.com>
Cc:	Andi Kleen <andi@...stfloor.org>,
	Peter Zijlstra <peterz@...radead.org>,
	LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake

Andi,

On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen <ak@...ux.intel.com> wrote:
>> I believe this mask of 0x3fff17 is wrong and should instead be
>> 0x7fffff based on the description of the FRONTEND
>> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
>> valid latency values may be rejected.
>
> No, my mask is correct.
>
Ok, so your event mask (0x17) really only allows what's defined
instead the full width of the field.

As for the IDQ_BUBBLE_WIDTH, you only allow 2 bits out of 3, so
maximum bubble threshold is 3
instead of 7. I assume this is because you know that it cannot have
more than 3 simultaneously then.

Would be good to explain this a bit more in the code.

> --
> ak@...ux.intel.com -- Speaking for myself only
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