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Message-ID: <20150717210537.GS19282@twins.programming.kicks-ass.net>
Date: Fri, 17 Jul 2015 23:05:37 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Andi Kleen <andi@...stfloor.org>
Cc: Stephane Eranian <eranian@...gle.com>,
Andi Kleen <ak@...ux.intel.com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake
On Fri, Jul 17, 2015 at 10:52:33PM +0200, Andi Kleen wrote:
>
> I don't think the code is the right place to document such registers.
If the code deviates from the SDM, it _is_ the right place to explain,
seeing how its the only place.
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