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Message-ID: <CABPqkBQH4bO6DpVfTQc3bR7vxpdr=kQoPT6VvzdMa+jqMRrLNg@mail.gmail.com>
Date:	Fri, 17 Jul 2015 15:00:18 -0700
From:	Stephane Eranian <eranian@...gle.com>
To:	Andi Kleen <ak@...ux.intel.com>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Andi Kleen <andi@...stfloor.org>,
	Peter Zijlstra <peterz@...radead.org>,
	LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake

Andi,

On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen <ak@...ux.intel.com> wrote:
>> But then, the SDM is misleading. It is not describing what's
>> implemented for SKL.
>
> Actually it has a list of valid values you can put into the various fields.
> None of them have the bits set you're trying to set.
>
You are talking about the events (bit 0-7). I am talking about the bubble
thresholds. I am okay with the event list for bits 0-7.

> -Andi
>
> --
> ak@...ux.intel.com -- Speaking for myself only
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