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Message-ID: <20150718004749.GV30412@codeaurora.org>
Date: Fri, 17 Jul 2015 17:47:49 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: James Liao <jamesjj.liao@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
Mike Turquette <mturquette@...libre.com>,
Heiko Stubner <heiko@...ech.de>, srv_heupstream@...iatek.com,
Daniel Kurtz <djkurtz@...omium.org>,
Ricky Liang <jcliang@...omium.org>,
Rob Herring <robh+dt@...nel.org>,
Sascha Hauer <kernel@...gutronix.de>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow
On 07/10, James Liao wrote:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
>
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
>
> Signed-off-by: James Liao <jamesjj.liao@...iatek.com>
> ---
Applied to clk-next
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