linux-kernel - Re: [PATCH] PCI: xilinx: Add check for MSI interrupt flag before handling as INTx

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Message-ID: <55AE73F3.8050600@xilinx.com>
Date:	Tue, 21 Jul 2015 18:31:47 +0200
From:	Michal Simek <michal.simek@...inx.com>
To:	Bjorn Helgaas <bhelgaas@...gle.com>,
	Russell Joyce <russell.joyce@...k.ac.uk>
CC:	michal.simek@...inx.com, soren.brinkmann@...inx.com,
	sthokal@...inx.com, jiang.liu@...ux.intel.com, arnd@...db.de,
	tglx@...utronix.de, wangyijing@...wei.com, wsa@...-dreams.de,
	robh@...nel.org, linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: xilinx: Add check for MSI interrupt flag before
 handling as INTx

Hi Bjorn,

On 07/21/2015 05:40 PM, Bjorn Helgaas wrote:
> On Tue, Jul 07, 2015 at 05:54:19PM +0100, Russell Joyce wrote:
>> Occasionally both MSI and INTx bits in the interrupt decode register are
>> set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the
>> interrupt message should be checked to ensure that the correct handler is
>> used.
>>
>> If this check is not in place and the interrupt message type is MSI, the
>> INTx handler will be used erroneously when both type bits are set.
>> This will also be followed by a second read of the message FIFO, which can
>> result in the function returning early and the interrupt decode register
>> not being cleared if the FIFO is now empty.
>>
>> Signed-off-by: Russell Joyce <russell.joyce@...k.ac.uk>
> 
> Applied to pci/host-xilinx for v4.3, thanks.
> 
> Xilinx guys, speak up if there's any issue with this.


I had 2 weeks off and still catching on emails. I will try to test this
and let you know if there is any problem.

Thanks,
Michal
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