linux-kernel - [PATCH] clk: socfpga: Add a second parent option for the dbg_base

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Message-ID: <1437591858-12552-1-git-send-email-dinguyen@opensource.altera.com>
Date:	Wed, 22 Jul 2015 14:04:18 -0500
From:	<dinguyen@...nsource.altera.com>
To:	<sboyd@...eaurora.org>, <mturquette@...libre.com>
CC:	<dinh.linux@...il.com>, <linux-clk@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>
Subject: [PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen <dinguyen@...nsource.altera.com>

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
---
 arch/arm/boot/dts/socfpga.dtsi   |  2 +-
 drivers/clk/socfpga/clk-periph.c | 18 ++++++++++++++----
 drivers/clk/socfpga/clk.h        |  1 +
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 80f924d..7d5db54 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -164,7 +164,7 @@
 						dbg_base_clk: dbg_base_clk {
 							#clock-cells = <0>;
 							compatible = "altr,socfpga-perip-clk";
-							clocks = <&main_pll>;
+							clocks = <&main_pll>, <&osc1>;
 							div-reg = <0xe8 0 9>;
 							reg = <0x50>;
 						};
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 0c66863..52c883e 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -44,8 +44,17 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
+static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
+{
+	u32 clk_src;
+
+	clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
+	return clk_src & 0x1;
+}
+
 static const struct clk_ops periclk_ops = {
 	.recalc_rate = clk_periclk_recalc_rate,
+	.get_parent = clk_periclk_get_parent,
 };
 
 static __init void __socfpga_periph_init(struct device_node *node,
@@ -55,7 +64,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
 	struct clk *clk;
 	struct socfpga_periph_clk *periph_clk;
 	const char *clk_name = node->name;
-	const char *parent_name;
+	const char *parent_name[SOCFPGA_MAX_PARENTS];
 	struct clk_init_data init;
 	int rc;
 	u32 fixed_div;
@@ -89,9 +98,10 @@ static __init void __socfpga_periph_init(struct device_node *node,
 	init.name = clk_name;
 	init.ops = ops;
 	init.flags = 0;
-	parent_name = of_clk_get_parent_name(node, 0);
-	init.parent_names = &parent_name;
-	init.num_parents = 1;
+
+	init.num_parents = of_clk_parent_fill(node, parent_name,
+					      SOCFPGA_MAX_PARENTS);
+	init.parent_names = parent_name;
 
 	periph_clk->hw.hw.init = &init;
 
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index aa2741d..814c724 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -22,6 +22,7 @@
 /* Clock Manager offsets */
 #define CLKMGR_CTRL		0x0
 #define CLKMGR_BYPASS		0x4
+#define CLKMGR_DBCTRL		0x10
 #define CLKMGR_L4SRC		0x70
 #define CLKMGR_PERPLL_SRC	0xAC
 
-- 
2.4.5

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