linux-kernel - Re: [PATCH 1/2] genirq: add chip_{suspend,resume} PM support to irq

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Message-ID: <20150722232831.GC8876@google.com>
Date:	Wed, 22 Jul 2015 16:28:31 -0700
From:	Brian Norris <computersforpeace@...il.com>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	Florian Fainelli <fainelli@...adcom.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Gregory Fong <gregory.0xf0@...il.com>,
	bcm-kernel-feedback-list@...adcom.com,
	linux-kernel@...r.kernel.org, linux-mips@...ux-mips.org,
	Kevin Cernekee <cernekee@...il.com>,
	Jason Cooper <jason@...edaemon.net>
Subject: Re: [PATCH 1/2] genirq: add chip_{suspend,resume} PM support to
 irq_chip

On Tue, Jul 21, 2015 at 11:58:01PM +0200, Thomas Gleixner wrote:
> On Tue, 21 Jul 2015, Florian Fainelli wrote:
> > On 21/07/15 14:23, Thomas Gleixner wrote:
> > > I just read back on the problem report which was mentioned in the
> > > changelog:
> > > 
> > > "It's not a problem with patch 7, exactly, it's a problem with the
> > >  irqchip driver which handles the UART interrupt mask (irq-bcm7120-l2.c).
> > >  The problem is that with a trimmed down device tree (such as the one
> > >  found at arch/arm/boot/dts/bcm7445-bcm97445svmb.dtb), none of the child
> > >  interrupts of the 'irq0_intc' node are described -- we don't have device
> > >  tree nodes for them yet -- but we still require saving and restoring the
> > >  forwarding mask (see 'brcm,int-fwd-mask') in order for the UART
> > >  interrupts to continue operating."
> > > 
> > > So you are trying to work around a flaw in the device tree by adding
> > > random callbacks to the core kernel?
> > 
> > Not quite, you could have your interrupt controller node declared in
> > Device Tree, but have no "interrupts" property referencing it because:
> > 
> > - the hardware is just not there, but you inherit a common Device Tree
> > skleten (*.dtsi)
> > - you could have Device Tree overlays which may or may not be loaded as
> > a result of finding expansion boards etc...
> 
> So if no hardware is there which uses any of those interrupts, then
> WHY is it a problem at all?

This particular badly-designed L2 interrupt controller not only
configures its own constituent interrupts, but it controls whether some
interrupts are seen at level 1 (e.g., GIC), rather than L2. So some
interrupts are affected, but not owned, by this hardware (and driver).

> If it's a requirement that these registers must be restored (once, not
> per irq), then I can see that it'd be nice to do that from the core.

Right, they must be restored for the whole chip.

> Though that core suspend/resume function is generic chip specific. So
> it does not make any sense to force it into struct irq_chip because we
> have no core infrastructure to deal with it.

Right, and that's what v2 does.

Thanks for the comments.

Brian
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