linux-kernel - Re: [PATCH v9 2/7] staging: usage documentation for simple fpga bus

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Message-ID: <20150723064338.GB23318@amd>
Date:	Thu, 23 Jul 2015 08:43:39 +0200
From:	Pavel Machek <pavel@...x.de>
To:	atull@...nsource.altera.com
Cc:	gregkh@...uxfoundation.org, jgunthorpe@...idianresearch.com,
	hpa@...or.com, monstr@...str.eu, michal.simek@...inx.com,
	rdunlap@...radead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, pantelis.antoniou@...sulko.com,
	robh+dt@...nel.org, grant.likely@...aro.org, iws@...o.caltech.edu,
	linux-doc@...r.kernel.org, broonie@...nel.org, philip@...ister.org,
	rubini@...dd.com, s.trumtrar@...gutronix.de, jason@...edaemon.net,
	kyle.teske@...com, nico@...aro.org, balbi@...com,
	m.chehab@...sung.com, davidb@...eaurora.org, rob@...dley.net,
	davem@...emloft.net, cesarb@...arb.net, sameo@...ux.intel.com,
	akpm@...ux-foundation.org, linus.walleij@...aro.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	devel@...verdev.osuosl.org, Petr Cvek <petr.cvek@....cz>,
	delicious.quinoa@...il.com, dinguyen@...nsource.altera.com,
	yvanderv@...nsource.altera.com
Subject: Re: [PATCH v9 2/7] staging: usage documentation for simple fpga bus

On Fri 2015-07-17 10:51:12, atull@...nsource.altera.com wrote:
> From: Alan Tull <atull@...nsource.altera.com>
> 
> Add a document spelling out usage of the simple fpga bus.

> +The DT overlay includes bindings (documented in bindings/simple-fpga-bus.txt)
> +that specify:
> + * Which fpga manager to use

fpga->FPGA, globally.

> + * Which image file to load
> + * Flags indicating whether this this image is for full reconfiguration or
> +   partial.
> + * a list of resets that should be released.  These enable the FPGA bridges.
> + * child nodes specifying the devices that will be added with appropriate
> +   compatible strings, etc.

Either all entries in the list should start with big letter or none
should. Also . at end of line should be consistent.

> +   Sequence
> +   --------
> + 1. Load the DT overlay.  One convenient way to do that is to use Pantelis'
> +    handy configfs interface (more below).

Reader has no chance to know what Pantelis' configfs interface is, and
there's nothing below.

> + 2. The simple FPGA bus gets probed and will do the following:
> +    a. call the fpga manager core to program the FPGA
> +    b. release the FPGA bridges
> +    c. call of_platform_populate resulting in device drivers getting probed.
> +

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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