linux-kernel - Re: [PATCH 3/5] x86/entry: Merge 32-bit and 64-bit sysenter setup code

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Message-ID: <20150723120650.2257cd8c@gandalf.local.home>
Date:	Thu, 23 Jul 2015 12:06:50 -0400
From:	Steven Rostedt <rostedt@...dmis.org>
To:	Andy Lutomirski <luto@...nel.org>
Cc:	X86 ML <x86@...nel.org>, linux-kernel@...r.kernel.org,
	Willy Tarreau <w@....eu>, Borislav Petkov <bp@...en8.de>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <peterz@...radead.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [PATCH 3/5] x86/entry: Merge 32-bit and 64-bit sysenter setup
 code

On Thu, 23 Jul 2015 08:31:41 -0700
Andy Lutomirski <luto@...nel.org> wrote:


> -	if (!boot_cpu_has(X86_FEATURE_SEP))
> +	/*
> +	 * On 64-bit CPUs, enable SEP unconditionally.  On Intel CPUs,
> +	 * it works and we use it.  On AMD CPUs, the MSRs exist but EIP
> +	 * is truncated to 32 bits.  This doesn't matter because AMD
> +	 * CPUs disallow SYSENTER in long mode.  If AMD ever decides to
> +	 * support SYSENTER, then they'll have to fix the truncation
> +	 * issue, and this code will work as-is.
> +	 */
> +
> +	if (IS_ENABLED(CONFIG_X86_32) && !boot_cpu_has(X86_FEATURE_SEP))
>  		goto out;
>  
> +#ifdef CONFIG_X86_32
>  	/*
>  	 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
>  	 * see the big comment in struct x86_hw_tss's definition.
>  	 */
>  	tss->x86_tss.ss1 = __KERNEL_CS;
> +#endif
>  
>  	wrmsrl_safe(MSR_IA32_SYSENTER_CS, __KERNEL_CS);
>  	wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
>  		    (unsigned long)tss +
>  		    offsetofend(struct tss_struct, SYSENTER_stack));
> +#ifdef CONFIG_X86_32
>  	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32);
> +#else
> +	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_compat);
> +#endif

As an additional clean up, what impact would we have to just rename
entry_SYSENTER_compat to entry_SYSENTER_32 on x86_64? It would remove
the need for the above #ifdef logic.

-- Steve


>  
>  out:
>  	put_cpu();
> @@ -1187,17 +1201,7 @@ void syscall_init(void)
>  
>  #ifdef CONFIG_IA32_EMULATION
>  	wrmsrl(MSR_CSTAR, entry_SYSCALL_compat);
> -	/*
> -	 * This only works on Intel CPUs.
> -	 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
> -	 * This does not cause SYSENTER to jump to the wrong location, because
> -	 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
> -	 */
> -	wrmsrl_safe(MSR_IA32_SYSENTER_CS, __KERNEL_CS);
> -	wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
> -		    (unsigned long)&per_cpu(cpu_tss, smp_processor_id()) +
> -		    offsetofend(struct tss_struct, SYSENTER_stack));
> -	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_compat);
> +	enable_sep_cpu();
>  #else
>  	wrmsrl(MSR_CSTAR, ignore_sysret);
>  	wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);

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