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Message-ID: <20150724092720.GA1597@katana>
Date: Fri, 24 Jul 2015 11:27:20 +0200
From: Wolfram Sang <wsa@...-dreams.de>
To: Andrey Danin <danindrey@...l.ru>
Cc: devicetree@...r.kernel.org, devel@...uxdriverproject.org,
linux-i2c@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
ac100@...ts.launchpad.net, Laxman Dewangan <ldewangan@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
Stephen Warren <swarren@...dotorg.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Julian Andres Klode <jak@...-linux.org>,
Marc Dietrich <marvin24@....de>
Subject: Re: [PATCH v3 1/4] i2c: tegra: implement slave mode
Hi Andrey,
On Mon, Jul 20, 2015 at 11:35:43PM +0300, Andrey Danin wrote:
> Initialization code is based on NVEC driver.
>
> There is a HW bug in AP20 that was also mentioned in kernel sources
> for Toshiba AC100.
>
> Signed-off-by: Andrey Danin <danindrey@...l.ru>
Still doesn't work for me and I think I understand why. Do you run your
I2C controller in slave mode only? That might work, but using it in
master/slave mode simultanously won't work yet as I see it:
* After every transfer (as master), clocks get disabled. I assume the IP
core won't be able to detect its own address then.
* There is this code in tegra_i2c_init():
if (!i2c_dev->is_dvc) {
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
}
It probably messes up the slave initialization in tegra_reg_slave().
At least I see that the slave address gets overwritten when I peek
the register after boot.
Does that make sense to you?
Thanks,
Wolfram
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