From e305b9a9cd80e56aeaa19b3c2a5bb26ba3adf8d7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 24 Jul 2015 10:10:23 +0200 Subject: [PATCH 1/2] mtd: spi-nor: Fix SRAM config on CQSPI Make sure the SRAM configuration register is loaded with correct data when initializing the controller. This might not always be the case, since for example U-Boot configures this register and even toggling the controller reset doesn't reset it to default value. Thus, explicitly set the register. Signed-off-by: Marek Vasut --- drivers/mtd/spi-nor/cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index fa7b421..a18732c 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1100,6 +1100,9 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) /* Disable all interrupts. */ writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); + /* Configure the SRAM split to 1:1 . */ + writel(0x40, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + cqspi_controller_enable(cqspi); } -- 2.1.4