lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <55B28BD4.2050403@codeaurora.org>
Date:	Fri, 24 Jul 2015 12:02:44 -0700
From:	"Zhang, Jonathan Zhixiong" <zjzhang@...eaurora.org>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	Will Deacon <Will.Deacon@....com>,
	"fu.wei@...aro.org" <fu.wei@...aro.org>,
	"al.stone@...aro.org" <al.stone@...aro.org>,
	"bp @ alien8 . de Matt Fleming" <matt.fleming@...el.com>,
	"rjw@...ysocki.net" <rjw@...ysocki.net>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linaro-acpi@...ts.linaro.org" <linaro-acpi@...ts.linaro.org>
Subject: Re: [PATCH V7 3/5] arm64: mm: add PROT_DEVICE_nGnRnE and
 PROT_NORMAL_WT

On 7/24/2015 9:15 AM, Catalin Marinas wrote:
> On Tue, Jul 21, 2015 at 10:59:18PM +0100, Jonathan (Zhixiong) Zhang wrote:
>> From: "Jonathan (Zhixiong) Zhang" <zjzhang@...eaurora.org>
>>
>> UEFI spec 2.5 section 2.3.6.1 defines that EFI_MEMORY_[UC|WC|WT|WB] are
>> possible EFI memory types for AArch64. Each of those EFI memory types
>> is mapped to a corresponding AArch64 memory type. So we need to define
>> PROT_DEVICE_nGnRnE and PROT_NORMWL_WT.
>>
>> MT_NORMAL_WT is defined, and its encoding is added to MAIR_EL1 when
>> initializing cpu.
>>
>> Change-Id: I20ac71ddf74c17e41769ecbb5f8c60eeefbb398a
>> Signed-off-by: Jonathan (Zhixiong) Zhang <zjzhang@...eaurora.org>
>
> I'll let the EFI guys to comment on whether these are needed, what for
> (we could probably live just fine only with Device nGnRE and Normal NC).
>
>>   #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>> index 838266f5b056..23e265d732f8 100644
>> --- a/arch/arm64/mm/proc.S
>> +++ b/arch/arm64/mm/proc.S
>> @@ -294,7 +294,7 @@ ENTRY(__cpu_setup)
>>   	msr	cpacr_el1, x0			// Enable FP/ASIMD
>>   	msr	mdscr_el1, xzr			// Reset mdscr_el1
>>   	/*
>> -	 * Memory region attributes for LPAE:
>> +	 * Memory region attributes for LPAE and EFI:
>
> LPAE refers to the page table format, the comment probably inherited
> from arch/arm. EFI means a completely different thing, so please remove
> it.
Yes, it was inherited from arch/arm/mm/proc-v7-3level.S. I'll remove
the change. That being said, the original statement is not totally
accurate I think, so if you prefer, I could change it like following.
-	 * Memory region attributes for LPAE:
+	 * Set MAIR with memory region attributes:

-- 
Jonathan (Zhixiong) Zhang
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ