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Message-ID: <20150727113622.GE29945@e104818-lin.cambridge.arm.com>
Date: Mon, 27 Jul 2015 12:36:22 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Duc Dang <dhdang@....com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
Tanmay Inamdar <tinamdar@....com>,
linux-arm <linux-arm-kernel@...ts.infradead.org>,
linux-kernel@...r.kernel.org
Subject: Re: X-Gene: Unhandled fault: synchronous external abort in
pci_generic_config_read32
On Fri, Jul 24, 2015 at 05:05:19PM -0700, Duc Dang wrote:
> On Fri, Jul 24, 2015 at 3:42 PM, Bjorn Helgaas <bhelgaas@...gle.com> wrote:
> > I regularly see faults like this on an APM X-Gene:
> >
> > U-Boot 2013.04-mustang_sw_1.14.14 (Dec 16 2014 - 15:59:33)
> > CPU0: APM ARM 64-bit Potenza Rev B0 2400MHz PCP 2400MHz
> > 32 KB ICACHE, 32 KB DCACHE
> > SOC 2000MHz IOBAXI 400MHz AXI 250MHz AHB 200MHz GFC 125MHz
> > ...
> > Unhandled fault: synchronous external abort (0x96000010) at 0xffffff8000110034
That's generated by an external device (PCIe root complex, card etc.)
and some mis-configured CPU setting.
> > Internal error: : 96000010 [#1] SMP
> > Modules linked in:
> > CPU: 0 PID: 3723 Comm: ... 4.1.0-smp-DEV #3
> > Hardware name: APM X-Gene Mustang board (DT)
> > task: ffffffc7dc1a4140 ti: ffffffc7dc118000 task.ti: ffffffc7dc118000
> > PC is at pci_generic_config_read32+0x4c/0xb8
> > LR is at pci_generic_config_read32+0x40/0xb8
> > pc : [<ffffffc00033b90c>] lr : [<ffffffc00033b900>] pstate: 600001c5
> > ...
> > Call trace:
> > [<ffffffc00033b90c>] pci_generic_config_read32+0x4c/0xb8
> > [<ffffffc00033bf58>] pci_user_read_config_byte+0x60/0xc4
> > [<ffffffc0003496a8>] pci_read_config+0x15c/0x238
> > [<ffffffc0002393b4>] sysfs_kf_bin_read+0x68/0xa0
> > [<ffffffc00023896c>] kernfs_fop_read+0x9c/0x1ac
> > [<ffffffc0001c361c>] __vfs_read+0x44/0x128
> > [<ffffffc0001c3e28>] vfs_read+0x84/0x144
> > [<ffffffc0001c4764>] SyS_read+0x50/0xb0
>
> The log shows kernel gets an exception when trying to access Mellanox
> card configuration space. This is usually due to suboptimal PCIe
> SerDes parameters are using in your board, which will cause bad link
> quality.
I would have hoped that "suboptimal" means that it still works, albeit
not fully optimal ;).
> The PCIe SerDes programming is done in U-Boot, so I suggest you do a
> U-Boot upgrade to our latest X-Gene U-Boot release.
>
> In order to access latest X-Gene U-Boot release, please use APM
> official support channel:
> https://myapm.apm.com
>
> Please register an account at myapm.apm.com if you don't have one
> using following link:
> https://myapm.apm.com/user/register
Isn't the latest U-Boot source for X-Gene publicly available anywhere?
It's GPL code anyway, so it shouldn't have proprietary code to require
registration, click-through agreements.
--
Catalin
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