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Message-ID: <1438023444-11881-3-git-send-email-dinguyen@opensource.altera.com>
Date:	Mon, 27 Jul 2015 13:57:22 -0500
From:	<dinguyen@...nsource.altera.com>
To:	<p.zabel@...gutronix.de>
CC:	<dinh.linux@...il.com>, <robh+dt@...nel.org>,
	<ijc+devicetree@...lion.org.uk>, <galak@...eaurora.org>,
	<mark.rutland@....com>, <pawel.moll@....com>,
	<s.trumtrar@...gutronix.de>, <linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>
Subject: [PATCH 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

From: Dinh Nguyen <dinguyen@...nsource.altera.com>

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
---
 Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++
 arch/arm/boot/dts/socfpga.dtsi                            | 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi                    | 1 +
 3 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
index 32c1c8b..98c9f56 100644
--- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
 Required properties:
 - compatible : "altr,rst-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
 - #reset-cells: 1
 
 Example:
@@ -10,4 +11,5 @@ Example:
 		#reset-cells = <1>;
 		compatible = "altr,rst-mgr";
 		reg = <0xffd05000 0x1000>;
+		altr,modrst-offset = <0x10>;
 	};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6..0bda96a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -783,6 +783,7 @@
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
 			reg = <0xffd05000 0x1000>;
+			altr,modrst-offset = <0x10>;
 		};
 
 		usbphy0: usbphy@0 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a252905..22e7d82 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,6 +593,7 @@
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
 			reg = <0xffd05000 0x100>;
+			altr,modrst-offset = <0x20>;
 		};
 
 		scu: snoop-control-unit@...fc000 {
-- 
2.4.5

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