lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Tue, 28 Jul 2015 16:52:04 +0200
From:	Michal Suchanek <hramrach@...il.com>
To:	Marek Vasut <marex@...x.de>
Cc:	David Woodhouse <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	Rafał Miłecki <zajec5@...il.com>,
	Huang Shijie <shijie.huang@...el.com>,
	Ben Hutchings <ben@...adent.org.uk>,
	Bean Huo 霍斌斌 (beanhuo) 
	<beanhuo@...ron.com>,
	MTD Maling List <linux-mtd@...ts.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] mtd: spi-nor: Add GD25LQ32C 1.8V SPI NOR flash ID

On 28 July 2015 at 16:38, Marek Vasut <marex@...x.de> wrote:
> On Tuesday, July 28, 2015 at 04:36:29 PM, Michal Suchanek wrote:
>> On 28 July 2015 at 16:33, Marek Vasut <marex@...x.de> wrote:
>> > On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
>> >> This 1.8V SPI NOR flash is found on ARM Chromebook XE303C and reads
>> >> something like 25LQ32VIG in the middle.
>> >>
>> >> Signed-off-by: Michal Suchanek <hramrach@...il.com>
>> >> ---
>> >>
>> >>  drivers/mtd/spi-nor/spi-nor.c | 1 +
>> >>  1 file changed, 1 insertion(+)
>> >>
>> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c
>> >> b/drivers/mtd/spi-nor/spi-nor.c index d78831b..cba3bd0 100644
>> >> --- a/drivers/mtd/spi-nor/spi-nor.c
>> >> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> >> @@ -559,6 +559,7 @@ static const struct spi_device_id spi_nor_ids[] = {
>> >>
>> >>       /* GigaDevice */
>> >>       { "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64, SECT_4K) },
>> >>
>> >> +     { "gd25lq32c", INFO(0xc86016, 0, 64 * 1024,  64, SECT_4K) },
>> >>
>> >>       { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
>> >>       { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
>> >
>> > Don't we have DT bindings, so we can use jedec,spi-nor prop for all
>> > new SPI NORs without growing this table ?
>>
>> When jedec,spi-nor compatible is used an attempt is made to identify
>> the chip using this table.
>>
>> When the ID is not in the table (or is misread due to transfer error)
>> spi-nor probe fails.
>
> Dang, I was under the impression we want to avoid growing this table :(
>

The table not to be grown is the devicetree compatibles table.
jedec,spi-nor should be enough for chips that respond to the ID
command.

BTW jedec is not a registered vendor and adding flash chips to
devicetree causes checkpatch warnings.

Theoretically you could use the ID data to infer block and whole flash
size but code for that is not in the driver. Not sure how many
vendor-specific encodings and exceptions are out there.

Thanks

Michal
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ