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Message-ID: <20150731103212.GB6218@nazgul.tnic>
Date: Fri, 31 Jul 2015 12:32:12 +0200
From: Borislav Petkov <bp@...en8.de>
To: Paolo Bonzini <pbonzini@...hat.com>
Cc: Andy Lutomirski <luto@...capital.net>,
Peter Zijlstra <peterz@...radead.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Willy Tarreau <w@....eu>, Steven Rostedt <rostedt@...dmis.org>,
X86 ML <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Brian Gerst <brgerst@...il.com>
Subject: Re: Dealing with the NMI mess
On Fri, Jul 31, 2015 at 12:26:34PM +0200, Paolo Bonzini wrote:
>
>
> On 31/07/2015 12:25, Borislav Petkov wrote:
> >> > The reason why it isn't documented is probably hidden within Intel.
> >> > Besides ICEBP, which is a bit fringe, there's no reason not to document
> >> > SALC which Thomas mentioned. SALC all has been there since the 8086,
> >> > and has been undocumented for thirty-odd years.
> > That one is invalid (on an IVB):
> >
> > [ 1306.231408] traps: icebp[3783] trap invalid opcode ip:4004b0 sp:7fffffffe610 error:0 in icebp[400000+1000]
> >
> > AMD APM documents it as invalid too.
>
> It's valid in 32-bit.
Yap, no invalid opcode there. I guess there's another bug in the APM's
opcode table then.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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