linux-kernel - Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll

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Message-ID: <55BB94A4.1010200@oracle.com>
Date:	Fri, 31 Jul 2015 08:30:44 -0700
From:	santosh shilimkar <santosh.shilimkar@...cle.com>
To:	Murali Karicheri <m-karicheri2@...com>, robh+dt@...nel.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	ssantosh@...nel.org, mturquette@...aro.org, sboyd@...eaurora.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-clk@...r.kernel.org, linux@....linux.org.uk,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div
 register for mainpll

On 7/31/2015 7:20 AM, Murali Karicheri wrote:
> On 05/29/2015 12:04 PM, Murali Karicheri wrote:
>> All of the keystone devices have a separate register to hold post
>> divider value for main pll clock. Currently the fixed-postdiv
>> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
>> use a value of 2 for this. Now that we have fixed this in the pll
>> clock driver change the dt bindings for the same.
>>
>> Signed-off-by: Murali Karicheri <m-karicheri2@...com>
>> ---

[..]

> Santosh,
>
> The clk driver update is already merged to v4.2-rc. Could you send this
> DT update as well for 4.2-rc?
>
Sure.

Regards,
Santosh
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