linux-kernel - Re: [PATCH] x86: serialize LVTT and TSC

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Message-ID: <20150802154948.GA1432307@devbig257.prn2.facebook.com>
Date:	Sun, 2 Aug 2015 08:49:49 -0700
From:	Shaohua Li <shli@...com>
To:	Thomas Gleixner <tglx@...utronix.de>
CC:	<x86@...nel.org>, <linux-kernel@...r.kernel.org>,
	<Kernel-team@...com>, Suresh Siddha <suresh.b.siddha@...el.com>,
	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...nel.org>,
	<stable@...r.kernel.org>
Subject: Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
> On Fri, 31 Jul 2015, Shaohua Li wrote:
> > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
> >  	apic_write(APIC_LVTT, lvtt_value);
> >  
> >  	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
> > +		u64 msr;
> > +
> > +		/*
> > +		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
> > +		 * writing APIC LVTT and TSC_DEADLINE MSR isn't serialized.
> > +		 * This uses the algorithm described in Intel SDM to serialize
> > +		 * the two writes
> > +		 * */
> > +		while (1) {
> > +			wrmsrl(MSR_IA32_TSC_DEADLINE, -1L);
> > +			rdmsrl(MSR_IA32_TSC_DEADLINE, msr);
> > +			if (msr)
> > +				break;
> > +		}
> > +		wrmsrl(MSR_IA32_TSC_DEADLINE, 0);
> 
> 
> I think this is exceptionally silly. A proper fence after the
> apic_write() should have the same effect.

Not sure what happens in the hardware, I could have a try of fence, but
I'd prefer using the algorithm Intel described. This is not a fast path,
the loop will exit immediately regardless the issue occurs anyway.

Thanks,
Shaohua
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