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Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
Date: Mon, 3 Aug 2015 10:38:18 +0530
From: Archit Taneja <architt@...eaurora.org>
To: linux-mtd@...ts.infradead.org, dehrenberg@...gle.com,
cernekee@...il.com, computersforpeace@...il.com
Cc: linux-arm-msm@...r.kernel.org, agross@...eaurora.org,
sboyd@...eaurora.org, linux-kernel@...r.kernel.org,
Archit Taneja <architt@...eaurora.org>,
devicetree@...r.kernel.org
Subject: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@...r.kernel.org
Signed-off-by: Archit Taneja <architt@...eaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..2e88eff 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,28 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@...00000 {
@@ -93,5 +115,19 @@
sata@...00000 {
status = "ok";
};
+
+ nand@...00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
+
+&adm_dma {
+ status = "ok";
+};
--
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