lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Tue, 4 Aug 2015 10:18:54 +0200
From:	Michal Simek <michal.simek@...inx.com>
To:	Philipp Zabel <p.zabel@...gutronix.de>,
	Moritz Fischer <moritz.fischer@...us.com>
CC:	<mark.rutland@....com>, <devicetree@...r.kernel.org>,
	<linux@....linux.org.uk>, <pawel.moll@....com>,
	<ijc+devicetree@...lion.org.uk>, <michal.simek@...inx.com>,
	<linux-kernel@...r.kernel.org>, <robh+dt@...nel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <galak@...eaurora.org>,
	<soren.brinkmann@...inx.com>
Subject: Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset
 Controller bindings.

On 08/04/2015 10:09 AM, Philipp Zabel wrote:
> Hi Moritz,
> 
> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer <moritz.fischer@...us.com>
>> ---
>>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> new file mode 100644
>> index 0000000..498c037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> @@ -0,0 +1,68 @@
>> +Xilinx Zynq Reset Manager
>> +
>> +The Zynq AP-SoC has several different resets.
>> +
>> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset"
>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> +- syscon: <&slcr>
>> +  This should be a phandle to the Zynq's SLCR register.
> 
>                                                  ^ register singular?
> 
> I still think the syscon phandle property is superfluous,
> but I'm fine with keeping it for consistency.
> It could always be made optional later.

Great.

Philipp: I expect you want to take at least 1/4 and 3/4 via your tree.
I am fine if you also want to add 2/4 and 4/4 via your tree.
If you think that they should go via arm-soc please let me know and I
will add them to the queue.

Thanks,
Michal
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ