linux-kernel - [tip:perf/core] perf/x86/intel: Handle new arch perfmon v4 status bits

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Date:	Tue, 4 Aug 2015 01:57:57 -0700
From:	tip-bot for Andi Kleen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	ak@...ux.intel.com, peterz@...radead.org, tglx@...utronix.de,
	mingo@...nel.org, hpa@...or.com, torvalds@...ux-foundation.org,
	linux-kernel@...r.kernel.org
Subject: [tip:perf/core] perf/x86/intel:
  Handle new arch perfmon v4 status bits

Commit-ID:  d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f
Gitweb:     http://git.kernel.org/tip/d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Sun, 10 May 2015 12:22:45 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Tue, 4 Aug 2015 10:16:57 +0200

perf/x86/intel: Handle new arch perfmon v4 status bits

ArchPerfmon v4 has some new status bits in GLOBAL_STATUS.

These need to be ignored when deciding whether a NMI
was an NMI, to avoid eating all NMIs when they
stay set, see:

    b292d7a10487 ("perf/x86/intel: ignore CondChgd bit to avoid false NMI handling")

This patch ignores the new ASIF bit, which indicates
that SGX interfered with the PMU, and also the new
LBR freezing bits, which are set when the LBRs get
frozen, plus the existing CondChange (set by JTAG
debuggers and some buggy BIOSes)

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: eranian@...gle.com
Link: http://lkml.kernel.org/r/1431285767-27027-8-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index cb112bf..52c9ded 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1611,13 +1611,14 @@ again:
 	intel_pmu_lbr_read();
 
 	/*
-	 * CondChgd bit 63 doesn't mean any overflow status. Ignore
-	 * and clear the bit.
+	 * Ignore a range of extra bits in status that do not indicate
+	 * overflow by themselves.
 	 */
-	if (__test_and_clear_bit(63, (unsigned long *)&status)) {
-		if (!status)
-			goto done;
-	}
+	status &= ~(GLOBAL_STATUS_COND_CHG |
+		    GLOBAL_STATUS_ASIF |
+		    GLOBAL_STATUS_LBRS_FROZEN);
+	if (!status)
+		goto done;
 
 	/*
 	 * PEBS overflow sets bit 62 in the global status register
--
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