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Message-ID: <CALCETrXffVT=KQpURGLEAXH5x6KxXhYuicGgk3hmF8-QGT81jw@mail.gmail.com>
Date: Tue, 4 Aug 2015 07:50:21 -0700
From: Andy Lutomirski <luto@...capital.net>
To: Thomas Gleixner <tglx@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"H. Peter Anvin" <hpa@...or.com>,
Andrew Lutomirski <luto@...nel.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Peter Zijlstra <peterz@...radead.org>,
"Liang, Kan" <kan.liang@...el.com>, Ingo Molnar <mingo@...nel.org>
Cc: "linux-tip-commits@...r.kernel.org"
<linux-tip-commits@...r.kernel.org>
Subject: Re: [tip:perf/core] perf/x86: Add an MSR PMU driver
On Tue, Aug 4, 2015 at 2:01 AM, tip-bot for Andy Lutomirski
<tipbot@...or.com> wrote:
> Commit-ID: b7b7c7821d932ba18ef6c8eafc8536066b4c2ef4
> Gitweb: http://git.kernel.org/tip/b7b7c7821d932ba18ef6c8eafc8536066b4c2ef4
> Author: Andy Lutomirski <luto@...nel.org>
I think I'm slightly late to the party reviewing what appears to be my
own code :)
> --- /dev/null
> +++ b/arch/x86/kernel/cpu/perf_event_msr.c
> @@ -0,0 +1,242 @@
> +#include <linux/perf_event.h>
> +
> +enum perf_msr_id {
> + PERF_MSR_TSC = 0,
> + PERF_MSR_APERF = 1,
> + PERF_MSR_MPERF = 2,
> + PERF_MSR_PPERF = 3,
> + PERF_MSR_SMI = 4,
> +
> + PERF_MSR_EVENT_MAX,
> +};
> +
> +struct perf_msr {
> + int id;
> + u64 msr;
> +};
> +
> +static struct perf_msr msr[] = {
> + { PERF_MSR_TSC, 0 },
> + { PERF_MSR_APERF, MSR_IA32_APERF },
> + { PERF_MSR_MPERF, MSR_IA32_MPERF },
> + { PERF_MSR_PPERF, MSR_PPERF },
> + { PERF_MSR_SMI, MSR_SMI_COUNT },
> +};
I think this could be easier to work with if it were [PERF_MSR_TSC] =
{...}, etc. No big deal, though, until the list gets long. However,
it might make fixing the apparent issue below easier...
> +static int msr_event_init(struct perf_event *event)
> +{
> + u64 cfg = event->attr.config;
...
> + event->hw.event_base = msr[cfg].msr;
Shouldn't this verify that the fancy enumeration code actually
believes that msr[cfg] exists on this system? Otherwise we might have
a very short wait until the perf fuzzer oopses this thing :)
--Andy
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